BibTeX records: Toru Fujimura

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@article{DBLP:journals/todaes/ChenFDNY16,
  author    = {Gong Chen and
               Toru Fujimura and
               Qing Dong and
               Shigetoshi Nakatake and
               Bo Yang},
  title     = {{DC} Characteristics and Variability on 90nm {CMOS} Transistor Array-Style
               Analog Layout},
  journal   = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume    = {21},
  number    = {3},
  pages     = {45:1--45:21},
  year      = {2016},
  url       = {https://doi.org/10.1145/2888395},
  doi       = {10.1145/2888395},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/journals/todaes/ChenFDNY16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LiuFYN10,
  author    = {Bo Liu and
               Toru Fujimura and
               Bo Yang and
               Shigetoshi Nakatake},
  title     = {{D-A} converter based variation analysis for analog layout design},
  booktitle = {Proceedings of the 15th Asia South Pacific Design Automation Conference,
               {ASP-DAC} 2010, Taipei, Taiwan, January 18-21, 2010},
  pages     = {843--848},
  publisher = {{IEEE}},
  year      = {2010},
  url       = {https://doi.org/10.1109/ASPDAC.2010.5419687},
  doi       = {10.1109/ASPDAC.2010.5419687},
  timestamp = {Wed, 12 Feb 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/aspdac/LiuFYN10.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/FujimuraN08,
  author    = {Toru Fujimura and
               Shigetoshi Nakatake},
  title     = {Transistor-level programmable {MOS} analog {IC} with body biasing},
  booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2008), 18-21
               May 2008, Sheraton Seattle Hotel, Seattle, Washington, {USA}},
  pages     = {153--156},
  publisher = {{IEEE}},
  year      = {2008},
  url       = {https://doi.org/10.1109/ISCAS.2008.4541377},
  doi       = {10.1109/ISCAS.2008.4541377},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/conf/iscas/FujimuraN08.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/NojimaONFOK06,
  author    = {Takashi Nojima and
               Nobuto Ono and
               Shigetoshi Nakatake and
               Toru Fujimura and
               Koji Okazaki and
               Yoji Kajitani},
  title     = {Adaptive Porting of Analog IPs with Reusable Conservative Properties},
  booktitle = {2006 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
               2006), 2-3 March 2006, Karlsruhe, Germany},
  pages     = {18--23},
  publisher = {{IEEE} Computer Society},
  year      = {2006},
  url       = {https://doi.org/10.1109/ISVLSI.2006.15},
  doi       = {10.1109/ISVLSI.2006.15},
  timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl    = {https://dblp.org/rec/conf/isvlsi/NojimaONFOK06.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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