15.2 A 350mV Single-Rail SRAM Using a Custom-Logic-Bitcell in 2nm-CMOS-Nanosheet Technology for Mobile and Edge-AI Applications.

Thu, 01 Jan 2026 00:00:00 +0100

Manish Trivedi, Sandipan Sinha, Ramesh Halli, Girishankar Gurumurthy, Jaswinder Singh, Chun-Yuan Cheng, Linchien Chen, Jeff Lin, Hugh Mair:
15.2 A 350mV Single-Rail SRAM Using a Custom-Logic-Bitcell in 2nm-CMOS-Nanosheet Technology for Mobile and Edge-AI Applications. ISSCC 2026: 256-258