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2010 – 2019
- 2018
[i1]Kapil Dev, Indrani Paul, Wei Huang, Yasuko Eckert, Wayne P. Burleson, Sherief Reda:
Implications of Integrated CPU-GPU Processors on Thermal and Power Management Techniques. CoRR abs/1808.09651 (2018)- 2017
- [j3]Yazhou Zu, Wei Huang, Indrani Paul, Vijay Janapa Reddi:
Ti-States: Power Management in Active Timing Margin Processors. IEEE Micro 37(3): 106-114 (2017) - [c19]Thiruvengadam Vijayaraghavan, Yasuko Eckert, Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Bradford M. Beckmann, William C. Brantley, Joseph L. Greathouse, Wei Huang, Arun Karunanithi, Onur Kayiran, Mitesh R. Meswani, Indrani Paul, Matthew Poremba, Steven Raasch, Steven K. Reinhardt, Greg Sadowski, Vilas Sridharan:
Design and Analysis of an APU for Exascale Computing. HPCA 2017: 85-96 - [c18]Abhinandan Majumdar, Leonardo Piga, Indrani Paul, Joseph L. Greathouse, Wei Huang, David H. Albonesi:
Dynamic GPGPU Power Management Using Adaptive Model Predictive Control. HPCA 2017: 613-624 - 2016
- [c17]Brian Kocoloski, Leonardo Piga, Wei Huang, Indrani Paul, John R. Lange:
A Case for Criticality Models in Exascale Systems. CLUSTER 2016: 213-216 - [c16]Hadi Asghari Moghaddam
, Hamid Reza Ghasemi, Abhishek Arvind Sinkar, Indrani Paul, Nam Sung Kim:
VR-scale: runtime dynamic phase scaling of processor voltage regulators for improving power efficiency. DAC 2016: 151:1-151:6 - [c15]Leonardo Piga, Indrani Paul, Wei Huang:
Performance Boosting Opportunities under Communication Imbalance in Power-Constrained HPC Clusters. ICPP 2016: 31-40 - [c14]Vignesh Adhinarayanan, Indrani Paul, Joseph L. Greathouse, Wei Huang, Ashutosh Pattnaik, Wu-chun Feng:
Measuring and modeling on-chip interconnect power on real hardware. IISWC 2016: 23-33 - [c13]Kapil Dev, Sherief Reda, Indrani Paul, Wei Huang, Wayne P. Burleson:
Workload-Aware Power Gating Design and Run-Time Management for Massively Parallel GPGPUs. ISVLSI 2016: 242-247 - [c12]Yazhou Zu, Wei Huang, Indrani Paul, Vijay Janapa Reddi:
Ti-states: Processor power management in the temperature inversion region. MICRO 2016: 55:1-55:13 - [c11]Kapil Dev, Indrani Paul, Wei Huang:
A framework for evaluating promising power efficiency techniques in future GPUs for HPC. SpringSim (HPS) 2016: 11 - 2015
- [j2]Michael J. Schulte, Mike Ignatowski, Gabriel H. Loh, Bradford M. Beckmann, William C. Brantley, Sudhanva Gurumurthi, Nuwan Jayasena, Indrani Paul, Steven K. Reinhardt, Gregory Rodgers:
Achieving Exascale Capabilities through Heterogeneous Computing. IEEE Micro 35(4): 26-36 (2015) - [c10]Manish Arora, Srilatha Manne, Indrani Paul, Nuwan Jayasena, Dean M. Tullsen:
Understanding idle behavior and power gating mechanisms in the context of modern benchmarks on CPU-GPU Integrated systems. HPCA 2015: 366-377 - [c9]Abhinandan Majumdar, Gene Y. Wu, Kapil Dev, Joseph L. Greathouse, Indrani Paul, Wei Huang, Arjun-Karthik Venugopal, Leonardo Piga, Chip Freitag, Sooraj Puthoor:
A Taxonomy of GPGPU Performance Scaling. IISWC 2015: 118-119 - [c8]Indrani Paul, Wei Huang, Manish Arora, Sudhakar Yalamanchili:
Harmonia: balancing compute and memory power in high-performance GPUs. ISCA 2015: 54-65 - 2014
- [j1]Indrani Paul, Vignesh T. Ravi, Srilatha Manne, Manish Arora, Sudhakar Yalamanchili:
Coordinated energy management in heterogeneous processors. Sci. Program. 22(2): 93-108 (2014) - [c7]Manish Arora, Srilatha Manne, Yasuko Eckert, Indrani Paul, Nuwan Jayasena, Dean M. Tullsen:
A comparison of core power gating strategies implemented in modern hardware. SIGMETRICS 2014: 559-560 - 2013
- [c6]Youngtaek Kim, Lizy Kurian John, Indrani Paul, Srilatha Manne, Michael J. Schulte:
Performance boosting under reliability and power constraints. ICCAD 2013: 334-341 - [c5]Indrani Paul, Srilatha Manne, Manish Arora, William Lloyd Bircher, Sudhakar Yalamanchili:
Cooperative boosting: needy versus greedy power management. ISCA 2013: 285-296 - [c4]Indrani Paul, Vignesh T. Ravi, Srilatha Manne, Manish Arora, Sudhakar Yalamanchili:
Coordinated energy management in heterogeneous processors. SC 2013: 59:1-59:12 - 2012
- [c3]Indrani Paul, Sudhakar Yalamanchili, Lizy K. John:
Performance impact of virtual machine placement in a datacenter. IPCCC 2012: 424-431
2000 – 2009
- 2002
- [c2]Indrani Paul, Sudhakar Yalamanchili, José Duato:
Algorithms for Switch-Scheduling in the Multimedia Router for LANs. HiPC 2002: 219-231 - [c1]Weidong Shi, Xiaotong Zhuang, Indrani Paul, Karsten Schwan:
Efficient Implementation of Packet Scheduling Algorithm on High-Speed Programmable Network Processors. MMNS 2002: 184-197
Coauthor Index
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