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ORCIDGennady Feygin
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2010 – 2019
- 2017
[j6]Mostafa El-Khamy
, Hessam Mahdavifar, Gennady Feygin, Jungwon Lee, Inyup Kang:
Relaxed Polar Codes. IEEE Trans. Inf. Theory 63(4): 1986-2000 (2017)- 2015
- [c9]Mostafa El-Khamy, Hessam Mahdavifar, Gennady Feygin, Jungwon Lee, Inyup Kang:
Relaxed channel polarization for reduced complexity polar coding. WCNC 2015: 207-212 - [i1]Mostafa El-Khamy, Hessam Mahdavifar, Gennady Feygin, Jungwon Lee, Inyup Kang:
Relaxed Polar Codes. CoRR abs/1501.06091 (2015) - 2010
- [c8]Jaimin Mehta, Robert Bogdan Staszewski, Oren E. Eliezer, Sameh Rezeq, Khurram Waheed, Mitch Entezari, Gennady Feygin, Sudheer K. Vemulapalli, Vasile Zoicas, Chih-Ming Hung, Nathen Barton, Imran Bashir, Kenneth Maggio, Michel Frechette, Meng-Chang Lee, John L. Wallberg, Patrick Cruise, Naveen K. Yanduru:
A 0.8mm2 all-digital SAW-less polar transmitter in 65nm EDGE SoC. ISSCC 2010: 58-59
2000 – 2009
- 2008
- [c7]Robert Bogdan Staszewski, Dirk Leipold, Oren E. Eliezer, Mitch Entezari, Khurram Muhammad, Imran Bashir, Chih-Ming Hung, John L. Wallberg, Roman Staszewski, Patrick Cruise, Sameh Rezeq, Sudheer K. Vemulapalli, Khurram Waheed, Nathen Barton, Meng-Chang Lee, Chan Fernando, Kenneth Maggio, Tom Jung, Imtinan Elahi, S. Larson, Thomas Murphy, Gennady Feygin, Irene Yuanying Deng, Terry Mayhugh Jr., Yo-Chuol Ho, K.-M. Low, Charles Lin, J. Jaehnig, J. Kerr, Jaimin Mehta, S. Glock, T. Almholt, Sumeer Bhatara:
A 24mm2 Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS. ISSCC 2008: 208-209 - 2006
- [j5]Robert Bogdan Staszewski, John L. Wallberg, Chih-Ming Hung, Gennady Feygin, Mitch Entezari, Dirk Leipold:
LMS-based calibration of an RF digitally controlled oscillator for mobile phones. IEEE Trans. Circuits Syst. II Express Briefs 53-II(3): 225-229 (2006) - 2001
- [c6]Gennady Feygin, Krishnaswamy Nagaraj, Ranjan Chattopadhyay, R. Herrera, I. Papantonopoulos, David A. Martin, P. Wu, Shanthi Pavan:
A 165 MS/s 8-bit CMOS A/D converter with background offset cancellation. CICC 2001: 153-156
1990 – 1999
- 1997
- [j4]Sami Kiriaki, T. Lakshmi Viswanathan, Gennady Feygin, Robert Bogdan Staszewski, Richard Pierson, Bill Krenik, Michiel de Wit, Krishnaswamy Nagaraj:
A 160-MHz analog equalizer for magnetic disk read Channel. IEEE J. Solid State Circuits 32(11): 1858-1865 (1997) - 1996
- [c5]David Yeh, Gennady Feygin, Paul Chow:
RACER: a reconfigurable constraint-length 14 Viterbi decoder. FCCM 1996: 60-69 - 1994
- [j3]Gennady Feygin, P. Glenn Gulak, Paul Chow:
Minimizing Excess Code Length and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding. Inf. Process. Manag. 30(6): 805-816 (1994) - [c4]Gennady Feygin, P. Glenn Gulak, Paul Chow:
Architectural Advances in the VLSI Implementation of Arithmetic Coding for Binary Image Compression. Data Compression Conference 1994: 254-263 - 1993
- [j2]Gennady Feygin, Patrick Glenn Gulak:
Architectural tradeoffs for survivor sequence memory management in Viterbi decoders. IEEE Trans. Commun. 41(3): 425-429 (1993) - [j1]Gennady Feygin, Patrick Glenn Gulak, Paul Chow:
A multiprocessor architecture for Viterbi decoders with linear speedup. IEEE Trans. Signal Process. 41(9): 2907-2917 (1993) - [c3]Gennady Feygin, P. Glenn Gulak, Paul Chow:
Minimizing Error and VLSI Complexity in the Multiplication-Free Approximation of Arithmetic Coding. Data Compression Conference 1993: 118-127 - [c2]Gennady Feygin, Paul Chow, P. Glenn Gulak, John Chappel, Grant Goodes, Oswin Hall, Ahmad Sayes, Satwant Singh, Michael B. Smith, Steven J. E. Wilton:
A VLSI Implementation of a Cascade Viterbi Decoder with Traceback. ISCAS 1993: 1945-1948 - 1991
- [c1]Gennady Feygin, Patrick Glenn Gulak, Paul Chow:
Generalized cascade Viterbi decoder-a locally connected multiprocessor with linear speed-up. ICASSP 1991: 1097-1100
Coauthor Index
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