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Ching-Tsun Chou
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2010 – 2019
- 2014
- [j8]Rakesh Komuravelli, Sarita V. Adve, Ching-Tsun Chou:
Revisiting the Complexity of Hardware Cache Coherence and Some Implications. ACM Trans. Archit. Code Optim. 11(4): 37:1-37:22 (2014) - 2011
- [c15]Byn Choi, Rakesh Komuravelli, Hyojin Sung, Robert Smolinski, Nima Honarmand, Sarita V. Adve, Vikram S. Adve, Nicholas P. Carter, Ching-Tsun Chou:
DeNovo: Rethinking the Memory Hierarchy for Disciplined Parallelism. PACT 2011: 155-166 - 2010
- [j7]Xiaofang Chen, Yu Yang, Ganesh Gopalakrishnan, Ching-Tsun Chou:
Efficient methods for formally verifying safety properties of hierarchical cache coherence protocols. Formal Methods Syst. Des. 36(1): 37-64 (2010)
2000 – 2009
- 2007
- [c14]Xiaofang Chen, Yu Yang, Michael Delisi, Ganesh Gopalakrishnan, Ching-Tsun Chou:
Hierarchical cache coherence protocol verification one level at a time through assume guarantee. HLDVT 2007: 107-114 - 2006
- [c13]Xiaofang Chen, Yu Yang, Ganesh Gopalakrishnan, Ching-Tsun Chou:
Reducing Verification Complexity of a Multicore Coherence Protocol Using Assume/Guarantee. FMCAD 2006: 81-88 - 2004
- [c12]Ching-Tsun Chou, Phanindra K. Mannava, Seungjoon Park:
A Simple Method for Parameterized Verification of Cache Coherence Protocols. FMCAD 2004: 382-398 - 2003
- [j6]Mani Azimi, Ching-Tsun Chou, Akhilesh Kumar, Victor W. Lee, Phanindra K. Mannava, Seungjoon Park:
Experience with Applying Formal Methods to Protocol Specification and System Architecture. Formal Methods Syst. Des. 22(2): 109-116 (2003) - 2001
- [c11]Kanna Shimizu, David L. Dill, Ching-Tsun Chou:
A Specification Methodology by a Collection of Compact Properties as Applied to the Intel® ItaniumTM Processor Bus Protocol. CHARME 2001: 340-354
1990 – 1999
- 1999
- [j5]Ching-Tsun Chou, Doron A. Peled:
Formal Verification of a Partial-Order Reduction Technique for Model Checking. J. Autom. Reason. 23(3-4): 265-298 (1999) - [c10]Ching-Tsun Chou:
The Mathematical Foundation fo Symbolic Trajectory Evaluation. CAV 1999: 196-207 - 1996
- [j4]Ching-Tsun Chou:
Simple Proof Techniques for Property Preservation via Simulation. Inf. Process. Lett. 60(3): 129-134 (1996) - [c9]Ching-Tsun Chou, Doron A. Peled:
Formal Verification of a Partial-Order Reduction Technique for Model Checking. TACAS 1996: 241-257 - 1995
- [j3]Ching-Tsun Chou:
Mechanical Verification of Distributed Algorithms in Higher-Order Logic. Comput. J. 38(2): 152-161 (1995) - 1994
- [c8]Ching-Tsun Chou:
A Formal Theory of Undirected Graphs in Higher-Order Logic. TPHOLs 1994: 144-157 - [c7]Ching-Tsun Chou:
Mechanical Verification of Distributed Algorithms in Higher-Order Logic. TPHOLs 1994: 158-176 - 1993
- [c6]Ching-Tsun Chou:
Predicates, Temporal Logic, and Simulations. HUG 1993: 310-323 - 1992
- [c5]Ching-Tsun Chou:
A Note on Interactive Theorem Proving with Theorem Continuation Functions. TPHOLs 1992: 59-69 - [c4]Ching-Tsun Chou:
A Sequent Formulation of a Logic of Predicates in HOL. TPHOLs 1992: 71-80 - 1990
- [j2]Ching-Tsun Chou, Israel Cidon, Inder S. Gopal, Shmuel Zaks:
Synchronizing asynchronous bounded delay networks. IEEE Trans. Commun. 38(2): 144-147 (1990)
1980 – 1989
- 1989
- [j1]Ching-Tsun Chou, Inder S. Gopal:
Linear Broadcast Routing. J. Algorithms 10(4): 490-517 (1989) - 1988
- [c3]Ching-Tsun Chou:
Linear Broadcast Routing. FSTTCS 1988: 122 - [c2]Ching-Tsun Chou, Eli Gafni:
Understanding and Verifying Distributed Algorithms Using Stratified Decomposition. PODC 1988: 44-65 - 1987
- [c1]Ching-Tsun Chou, Israel Cidon, Inder S. Gopal, Shmuel Zaks:
Synchronizing Aysnchronous Bounded Delay Networks. WDAG 1987: 212-218
Coauthor Index
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