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ORCIDYifan Wang 0001
Person information
- affiliation: RWTH Aachen University, Chair of Integrated Analog Circuits, Germany
Other persons with the same name
- Yifan Wang (aka: Yi-Fan Wang, Wang Yifan) — disambiguation page
- Yifan Wang 0002
![[0000-0002-2170-714X]](https://dblp.dagstuhl.de/img/orcid-mark.12x12.png "0000-0002-2170-714X")
— University of Tennessee, Department of Electrical Engineering and Computer Science, Knoxville, TN, USA - Yifan Wang 0003 — University of Queensland, School of ITEE, Brisbane, QLD, Australia
- Yifan Wang 0004 — Dalian University of Technology, School of Information and Communication Engineering, China
- Yifan Wang 0005 — Wayne State University, MI, USA
- Yifan Wang 0006 — Beijing University of Posts and Telecommunications, China
- Yifan Wang 0007 — Shanghai Jiao Tong University, Shanghai, China
- Yifan Wang 0008 — Central South University, Changsha, China
- Yifan Wang 0009 — Georgia Institute of Technology, Atlanta, GA, USA
- Yifan Wang 0010 — Universität des Saarlandes, Germany
- Yifan Wang 0011 (aka: Wang Yifan 0011) — Adobe Systems, San Jose, CA, USA (and 2 more)
- Yifan Wang 0012 — University of Florida, FL, USA
- Yifan Wang 0014 (aka: Yi-Fan Wang 0014) — Peking University, School of Computer Science, Beijing, China (and 1 more)
- Yifang Wang 0007 (aka: Yifan Wang 0015) — Tsinghua University, Department of Automation, Beijing, China
- Yifan Wang 0016 — JD AI Research, Beijing, China
- Yifan Wang 0017 — Tsinghua University, DCST, BNRist, Beijing, China
- Yifan Wang 0018 — University of Southern California, Media Communications Lab, Los Angeles, CA, USA
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2010 – 2019
- 2014
[c10]Zhimiao Chen, Yifan Wang, Lei Liao, Ye Zhang, Aytac Atac, Jan Henning Müller, Ralf Wunderlich, Stefan Heinen:
A SystemC Virtual Prototyping based Methodology for Multi-Standard SoC Functional Verification. DAC 2014: 59:1-59:6- [c9]Aytac Atac, Zhimiao Chen, Lei Liao, Yifan Wang, Martin Schleyer, Ye Zhang, Ralf Wunderlich, Stefan Heinen:
An HDL-Based System Design Methodology for Multistandard RF SoC's. DAC 2014: 167:1-167:6 - [c8]Lei Liao, Aytac Atac, Ye Zhang, Yifan Wang, Zhimiao Chen, Martin Schleyer, Ralf Wunderlich, Stefan Heinen:
A 1.2V, 2.7mA receiver front-end for bluetooth low energy applications. RWS 2014: 37-39 - 2013
- [j2]Ye Zhang, Yifan Wang, Ralf Wunderlich, Stefan Heinen:
A Novel Low-Effort Demodulator for Low Power Short Range Wireless Transceivers. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(9): 2521-2532 (2013) - [c7]Zhimiao Chen, Yifan Wang, Joern Driesen, Fabio Garzia, Stefan Koehler, Frank Henkel, Ralf Wunderlich, Stefan Heinen:
Comparison of modeling approaches through hierarchical behavioral modeling of a GNSS receiver front-end. CICC 2013: 1-4 - [c6]Aytac Atac, Lei Liao, Yifan Wang, Martin Schleyer, Ye Zhang, Ralf Wunderlich, Stefan Heinen:
A 1.7mW quadrature bandpass ΔΣ ADC with 1MHz BW and 60dB DR at 1MHz IF. ISCAS 2013: 1039-1042 - 2010
- [c5]Yifan Wang, Zhimiao Chen, Stefan Heinen:
Hierarchical generation of pin accurate SystemC models based on RF circuit schematics. BMAS 2010: 25-30
2000 – 2009
- 2009
- [j1]Yifan Wang, Stefan Joeres, Ralf Wunderlich, Stefan Heinen:
Modeling Approaches for Functional Verification of RF-SoCs: Limits and Future Requirements. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(5): 769-773 (2009) - [c4]Yifan Wang, Christoph van Meersbergen, Hans-Werner Groh, Stefan Heinen:
Event driven analog modeling for the verification of PLL frequency synthesizers. BMAS 2009: 25-30 - [c3]Erich Barke, Darius Grabowski, Helmut Graeb, Lars Hedrich, Stefan Heinen, Ralf Popp, Sebastian Steinhorst, Yifan Wang:
Formal approaches to analog circuit verification. DATE 2009: 724-729 - [c2]Yifan Wang, Ralf Wunderlich, Stefan Heinen, Hans-Werner Groh:
Event gesteuerte Modellierung analoger Frontends für die funktionale Verifikation des RF-SoCs. MBMV 2009: 237-246 - 2008
- [c1]Yifan Wang, Stefan Joeres, Ralf Wunderlich, Stefan Heinen:
Issues on View Switching for RF SoC Verification. BMAS 2008: 72-77
Coauthor Index
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