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Subodh Gupta
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2000 – 2009
- 2009
- [c5]Qiang Wang, Subodh Gupta, Jason Helge Anderson:
Clock power reduction for virtex-5 FPGAs. FPGA 2009: 13-22 - 2007
- [c4]Subodh Gupta, Jason Helge Anderson, Linda Farragher, Qiang Wang:
CAD Techniques for Power Optimization in Virtex-5 FPGAs. CICC 2007: 85-88 - 2003
- [j3]Subodh Gupta, Farid N. Najm:
Energy and peak-current per-cycle estimation at RTL. IEEE Trans. Very Large Scale Integr. Syst. 11(4): 525-537 (2003) - 2000
- [b1]Subodh Gupta:
Bottom-Up High-Level Power Modeling and Estimation. University of Illinois Urbana-Champaign, USA, 2000 - [j2]Subodh Gupta, Farid N. Najm:
Analytical models for RTL power estimation of combinational andsequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(7): 808-814 (2000) - [j1]Subodh Gupta, Farid N. Najm:
Power modeling for high-level power estimation. IEEE Trans. Very Large Scale Integr. Syst. 8(1): 18-29 (2000)
1990 – 1999
- 1999
- [c3]Subodh Gupta, Farid N. Najm:
Power macro-models for DSP blocks with application to high-level synthesis. ISLPED 1999: 103-105 - [c2]Subodh Gupta, Farid N. Najm:
Energy-per-cycle estimation at RTL. ISLPED 1999: 121-126 - 1997
- [c1]Subodh Gupta, Farid N. Najm:
Power Macromodeling for High Level Power Estimation. DAC 1997: 365-370
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