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ORCIDJ. Robert Heath
Person information
- affiliation: University of Kentucky, Department of Electrical and Computer Engineering, Lexington, KY, USA
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2010 – 2019
- 2011
[c14]Rishvanth Kora Venugopal, J. Robert Heath, Daniel L. Lau
:
FPGA based parallel architecture implementation of Stacked Error Diffusion algorithm. SASP 2011: 66-69- 2010
- [j8]Veerendra Bhargav Alluri, J. Robert Heath, Michael Lhamon:
A new multichannel, coherent amplitude modulated, time-division multiplexed, software-defined radio receiver architecture, and field-programmable-gate-array technology implementation. IEEE Trans. Signal Process. 58(10): 5369-5384 (2010)
2000 – 2009
- 2009
- [c13]J. Robert Heath, Nien Y. Lim, Kenneth L. Calvert, Jim Griffioen:
A New Reconfigurable Network Node Processor Architecture for Distributed Implementation of Ephemeral State Processing. PDCCS 2009: 213-220 - [c12]J. Robert Heath, Sridhar Hegde, Kanchan Bhide:
Development and Validation of a Load Balancing and Control Mechanism for a Reconfigurable Single-Chip Heterogenous and Hybrid Multiprocessor Architecture Platform. PDCCS 2009: 228-235 - 2008
- [c11]Phani Tangirala, J. Robert Heath, Arthur Radun, Terry Conners:
A Hand-Held Programmable-Logic-Device Based Temperature and Relative-Humidity Sensor, Processor and Display System Platform for Automation and Control of Industry Processes. IAS 2008: 1-8 - 2007
- [j7]Albert T. Wong, J. Robert Heath, Michael Lhamon:
New systolic array processor architecture for simultaneous discrete convolution of an image plane with multiple filter coefficient sets. J. Electronic Imaging 16(1): 013014 (2007) - 2004
- [c10]M. Muthulakshmi, J. Robert Heath, Kenneth L. Calvert, James Griffioen:
ESP: a flexible, high-performance, PLD-based network service. ICC 2004: 1014-1018 - 2001
- [c9]J. Robert Heath, Andrew Tan:
Modeling, Design, Virtual and Physical Prototyping, Testing, and Verification of a Multifunctional Processor Queue for a Single-Chip Multiprocessor Architecture. IEEE International Workshop on Rapid System Prototyping 2001: 128-135 - 2000
- [j6]J. Robert Heath, Peter Yakutis:
High speed storage area networks using a fibre channel arbitrated loop interconnect. IEEE Netw. 14(2): 51-56 (2000)
1990 – 1999
- 1997
- [j5]J. Robert Heath, Balasubramanian Sivanesa:
Development, Analysis, and Verification of a Parallel Hybrid Dataflow Computer Architectural Framework and Associated Load-Balancing Strategies and Algorithms via Parallel Simulation. Simul. 69(1): 7-25 (1997) - 1994
- [j4]Tae Won Cho, Sam S. Pyo, J. Robert Heath:
PARALLEX: a parallel approach to switchbox routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(6): 684-693 (1994) - 1992
- [c8]Tae Won Cho, Sam S. Pyo, J. Robert Heath:
A new conflict resolving switchbox router. Great Lakes Symposium on VLSI 1992: 95-102
1980 – 1989
- 1988
- [c7]J. Robert Heath, Eric Allen Disch:
A methodology for the control and custom VLSI implementation of large-scale Clos networks. ICCD 1988: 472-477 - 1986
- [j3]J. Robert Heath:
A note on "Realization of digital filters using input-scaled floating-point arithmetic". IEEE Trans. Acoust. Speech Signal Process. 34(4): 995 (1986) - 1984
- [c6]George Broomell, J. Robert Heath:
An Integrated-Circuit Crossbar Switching System Design. ICDCS 1984: 278-287 - 1983
- [j2]George Broomell, J. Robert Heath:
Classification Categories and Historical Development of Circuit Switching Topologies. ACM Comput. Surv. 15(2): 95-133 (1983) - 1982
- [c5]Andrew D. Hurt, J. Robert Heath:
The Design of a Fault-Tolerant Computing Element for Distributed Data Processors. ICDCS 1982: 171-176 - [c4]J. Robert Heath, George Broomell, Andrew D. Hurt:
A distributed computer architecture for real-time, data driven applications. ICDCS 1982: 630-638 - [c3]Andrew D. Hurt, J. Robert Heath:
A Hardware Task Scheduling Mechanism for a Real-Time Multi-Microprocessor Architecture. RTSS 1982: 113-123 - 1981
- [j1]J. Robert Heath, Shailesh Patel:
How to Write a Universal Cross-Assembler. IEEE Micro 1(3): 45-66 (1981) - 1980
- [c2]J. Robert Heath, James Cline:
The Complexity and Use of a Multistage Interconnection Network for Distributed Processing Systems. RTSS 1980: 28-35
1970 – 1979
- 1977
- [c1]J. Robert Heath, Bill D. Carroll, Terry T. Cwik:
CDL - A tool for concurrent hardware and software development. DAC 1977: 445-449
Coauthor Index
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