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2020 – today
- 2021
[c42]Chirag Sudarshan, Taha Soliman, Cecilia De la Parra, Christian Weis, Leonardo Ecco, Matthias Jung, Norbert Wehn, Andre Guntoro:
A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs. ASP-DAC 2021: 35-42- [c41]Matthias Jung, Christian Weis, Norbert Wehn:
The Dynamic Random Access Memory Challenge in Embedded Computing Systems. A Journey of Embedded and Cyber-Physical Systems 2021: 19-36 - 2020
- [j15]Mhd Rashed Al Koutayni
, Vladimir Rybalkin, Jameel Malik, Ahmed Elhayek, Christian Weis, Gerd Reis, Norbert Wehn, Didier Stricker:
Real-Time Energy Efficient Hand Pose Estimation: A Case Study. Sensors 20(10): 2828 (2020) - [j14]Vladimir Rybalkin, Chirag Sudarshan, Christian Weis, Jan Lappas, Norbert Wehn, Li Cheng:
Efficient Hardware Architectures for 1D- and MD-LSTM Networks. J. Signal Process. Syst. 92(11): 1219-1245 (2020) - [j13]Dimitrios Stathis, Chirag Sudarshan, Yu Yang, Matthias Jung, Christian Weis, Ahmed Hemani, Anders Lansner, Norbert Wehn:
eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex. J. Signal Process. Syst. 92(11): 1323-1343 (2020) - [c40]Éder F. Zulian, Christian Weis, Norbert Wehn:
Access-Aware Per-Bank DRAM Refresh for Reduced DRAM Refresh Overhead. ISCAS 2020: 1-5 - [i3]Jason Lowe-Power, Abdul Mutaal Ahmad, Ayaz Akram, Mohammad Alian, Rico Amslinger, Matteo Andreozzi, Adrià Armejach, Nils Asmussen, Srikant Bharadwaj, Gabe Black, Gedare Bloom, Bobby R. Bruce, Daniel Rodrigues Carvalho, Jerónimo Castrillón, Lizhong Chen, Nicolas Derumigny, Stephan Diestelhorst, Wendy Elsasser, Marjan Fariborz, Amin Farmahini Farahani, Pouya Fotouhi, Ryan Gambord, Jayneel Gandhi, Dibakar Gope, Thomas Grass, Bagus Hanindhito, Andreas Hansson, Swapnil Haria, Austin Harris, Timothy Hayes, Adrian Herrera, Matthew Horsnell, Syed Ali Raza Jafri, Radhika Jagtap, Hanhwi Jang, Reiley Jeyapaul, Timothy M. Jones, Matthias Jung, Subash Kannoth, Hamidreza Khaleghzadeh, Yuetsu Kodama, Tushar Krishna, Tommaso Marinelli, Christian Menard, Andrea Mondelli, Tiago Mück, Omar Naji, Krishnendra Nathella, Hoa Nguyen, Nikos Nikoleris, Lena E. Olson, Marc S. Orr, Binh Pham, Pablo Prieto, Trivikram Reddy, Alec Roelke, Mahyar Samani, Andreas Sandberg, Javier Setoain, Boris Shingarov, Matthew D. Sinclair, Tuan Ta, Rahul Thakur, Giacomo Travaglini, Michael Upton, Nilay Vaish, Ilias Vougioukas, Zhengrong Wang, Norbert Wehn, Christian Weis, David A. Wood, Hongil Yoon, Éder F. Zulian:
The gem5 Simulator: Version 20.0+. CoRR abs/2007.03152 (2020)
2010 – 2019
- 2019
- [c39]Chirag Sudarshan, Jan Lappas, Muhammad Mohsin Ghaffar, Vladimir Rybalkin, Christian Weis, Matthias Jung, Norbert Wehn:
An In-DRAM Neural Network Processing Engine. ISCAS 2019: 1-5 - [c38]Matthias Jung, Kira Kraft, Taha Soliman, Chirag Sudarshan, Christian Weis, Norbert Wehn:
Fast validation of DRAM protocols with timed petri nets. MEMSYS 2019: 133-147 - [c37]Deepak M. Mathew, André Lucas Chinazzo, Christian Weis, Matthias Jung, Bastien Giraud, Pascal Vivet, Alexandre Levisse, Norbert Wehn:
RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM. SAMOS 2019: 34-47 - [c36]Chirag Sudarshan, Jan Lappas, Christian Weis, Deepak M. Mathew, Matthias Jung, Norbert Wehn:
A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing. SAMOS 2019: 429-441 - [i2]Dimitrios Stathis, Chirag Sudarshan, Yu Yang, Matthias Jung, Syed Mohammad Asad Hassan Jafri, Christian Weis, Ahmed Hemani, Anders Lansner, Norbert Wehn:
eBrainII: A 3 kW Realtime Custom 3D DRAM integrated ASIC implementation of a Biologically Plausible Model of a Human Scale Cortex. CoRR abs/1911.00889 (2019) - 2018
- [j12]Christian Brugger, Valentin Grigorovici, Matthias Jung, Christian de Schryver, Christian Weis, Norbert Wehn, Katharina Anna Zweig:
A Memory Centric Architecture of the Link Assessment Algorithm in Large Graphs. IEEE Des. Test 35(1): 7-15 (2018) - [c35]Deepak M. Mathew, Martin Schultheis, Carl Christian Rheinländer, Chirag Sudarshan, Christian Weis, Norbert Wehn, Matthias Jung:
An analysis on retention error behavior and power consumption of recent DDR4 DRAMs. DATE 2018: 293-296 - [c34]Kira Kraft, Chirag Sudarshan, Deepak M. Mathew, Christian Weis, Norbert Wehn, Matthias Jung:
Improving the error behavior of DRAM by exploiting its Z-channel property. DATE 2018: 1492-1495 - [c33]Menbere Kina Tekleyohannes, Christian Weis, Norbert Wehn, Martin Klein, Michael Siegrist:
A Reconfigurable Accelerator for Morphological Operations. IPDPS Workshops 2018: 186-193 - [c32]Christian Weis, Matthias Jung, Éder F. Zulian, Chirag Sudarshan, Deepak M. Mathew, Norbert Wehn:
The Role of Memories in Transprecision Computing. ISCAS 2018: 1-5 - [c31]Kira Kraft, Deepak M. Mathew, Chirag Sudarshan, Matthias Jung, Christian Weis, Norbert Wehn, Florian Longnos:
Efficient coding scheme for DDR4 memory subsystems. MEMSYS 2018: 148-157 - [c30]Matthias Jung, Sally A. McKee, Chirag Sudarshan, Christoph Dropmann, Christian Weis, Norbert Wehn:
Driving into the memory wall: the role of memory for advanced driver assistance systems and autonomous driving. MEMSYS 2018: 377-386 - [i1]Radhika Jagtap, Matthias Jung, Wendy Elsasser, Christian Weis, Andreas Hansson, Norbert Wehn:
Integrating DRAM Power-Down Modes in gem5 and Quantifying their Impact. CoRR abs/1803.07613 (2018) - 2017
- [j11]Matthias Jung, Deepak M. Mathew, Carl Christian Rheinländer, Christian Weis, Norbert Wehn:
A Platform to Analyze DDR3 DRAM's Power and Retention Time. IEEE Des. Test 34(4): 52-59 (2017) - [j10]Pei Liu, Ahmed Hemani, Kolin Paul, Christian Weis, Matthias Jung, Norbert Wehn:
3D-Stacked Many-Core Architecture for Biological Sequence Analysis Problems. Int. J. Parallel Program. 45(6): 1420-1460 (2017) - [j9]Christian Weis, Abdul Mutaal, Omar Naji, Matthias Jung, Andreas Hansson, Norbert Wehn:
DRAMSpec: A High-Level DRAM Timing, Power and Area Exploration Tool. Int. J. Parallel Program. 45(6): 1566-1591 (2017) - [j8]Pei Liu, Ahmed Hemani, Kolin Paul, Christian Weis, Matthias Jung, Norbert Wehn:
A Customized Many-Core Hardware Acceleration Platform for Short Read Mapping Problems Using Distributed Memory Interface with 3D-Stacked Architecture. J. Signal Process. Syst. 87(3): 327-341 (2017) - [c29]Menbere Tekleyohannes, MohammadSadegh Sadri, Christian Weis, Norbert Wehn, Martin Klein, Michael Siegrist:
An advanced embedded architecture for connected component analysis in industrial applications. DATE 2017: 734-735 - [c28]Radhika Jagtap, Matthias Jung, Wendy Elsasser, Christian Weis, Andreas Hansson, Norbert Wehn:
Integrating DRAM power-down modes in gem5 and quantifying their impact. MEMSYS 2017: 86-95 - [c27]Deepak M. Mathew, Éder F. Zulian, Matthias Jung, Kira Kraft, Christian Weis, Bruce L. Jacob, Norbert Wehn:
Using run-time reverse-engineering to optimize DRAM refresh. MEMSYS 2017: 115-124 - [c26]Deepak M. Mathew, Éder F. Zulian, Subash Kannoth, Matthias Jung, Christian Weis, Norbert Wehn:
A Bank-Wise DRAM Power Model for System Simulations. RAPIDO 2017: 5 - 2016
- [j7]Matthias Jung, Christian Weis, Norbert Wehn:
A cross layer approach for efficient thermal management in 3D stacked SoCs. Microelectron. Reliab. 61: 43-47 (2016) - [c25]Matthias Jung, Deepak M. Mathew, Christian Weis, Norbert Wehn:
Efficient reliability management in SoCs - an approximate DRAM perspective. ASP-DAC 2016: 390-394 - [c24]Matthias Jung, Deepak M. Mathew, Christian Weis, Norbert Wehn:
Invited - Approximate computing with partially unreliable dynamic random access memory - approximate DRAM. DAC 2016: 100:1-100:4 - [c23]Philipp Schläfer, Chu-Hsiang Huang, Clayton Schoeny, Christian Weis, Yao Li, Norbert Wehn, Lara Dolecek:
Error resilience and energy efficiency: An LDPC decoder design study. DATE 2016: 588-593 - [c22]Matthias Jung, Deepak M. Mathew, Christian Weis, Norbert Wehn, Irene Heinrich, Marco V. Natale, Sven O. Krumke:
ConGen: An Application Specific DRAM Memory Controller Generator. MEMSYS 2016: 257-267 - [c21]Matthias Jung, Carl Christian Rheinländer, Christian Weis, Norbert Wehn:
Reverse Engineering of DRAMs: Row Hammer with Crosshair. MEMSYS 2016: 471-476 - [c20]Matthias Jung, Deepak M. Mathew, Éder F. Zulian, Christian Weis, Norbert Wehn:
A new bank sensitive DRAMPower model for efficient design space exploration. PATMOS 2016: 283-288 - 2015
- [j6]Matthias Jung, Christian Weis, Norbert Wehn:
DRAMSys: A Flexible DRAM Subsystem Design Space Exploration Framework. IPSJ Trans. Syst. LSI Des. Methodol. 8: 63-74 (2015) - [j5]Michael Glaß, Hananeh Aliee, Liang Chen, Mojtaba Ebrahimi, Faramarz Khosravi, Veit B. Kleeberger, Alexandra Listl, Daniel Müller-Gritschneder, Fabian Oboril, Ulf Schlichtmann, Mehdi Baradaran Tahoori, Jürgen Teich, Norbert Wehn, Christian Weis:
Application-aware cross-layer reliability analysis and optimization. it Inf. Technol. 57(3): 159-169 (2015) - [c19]Christian Weis, Matthias Jung, Peter Ehses, Cristiano Santos, Pascal Vivet, Sven Goossens, Martijn Koedam, Norbert Wehn:
Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs. DATE 2015: 495-500 - [c18]Christian Brugger, Valentin Grigorovici, Matthias Jung, Christian Weis, Christian de Schryver, Katharina Anna Zweig, Norbert Wehn:
A Custom Computing System for Finding Similarties in Complex Networks. ISVLSI 2015: 262-267 - [c17]Christian Weis, Matthias Jung, Omar Naji, Norbert Wehn, Cristiano Santos, Pascal Vivet, Andreas Hansson:
Thermal Aspects and High-Level Explorations of 3D Stacked DRAMs. ISVLSI 2015: 609-614 - [c16]Matthias Jung, Éder Zulian, Deepak M. Mathew, Matthias Herrmann, Christian Brugger, Christian Weis, Norbert Wehn:
Omitting Refresh: A Case Study for Commodity and Wide I/O DRAMs. MEMSYS 2015: 85-91 - [c15]Omar Naji, Christian Weis, Matthias Jung, Norbert Wehn, Andreas Hansson:
A high-level DRAM timing, power and area exploration tool. SAMOS 2015: 149-156 - 2014
- [j4]Andreas Herkersdorf, Hananeh Aliee, Michael Engel, Michael Glaß, Christina Gimmler-Dumont, Jörg Henkel, Veit Kleeberger, Michael A. Kochte, Johannes Maximilian Kühn, Daniel Mueller-Gritschneder, Sani R. Nassif, Holm Rauchfuss, Wolfgang Rosenstiel, Ulf Schlichtmann, Muhammad Shafique, Mehdi Baradaran Tahoori, Jürgen Teich, Norbert Wehn, Christian Weis, Hans-Joachim Wunderlich:
Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience. Microelectron. Reliab. 54(6-7): 1066-1074 (2014) - [c14]Karthik Chandrasekar, Sven Goossens, Christian Weis, Martijn Koedam, Benny Akesson, Norbert Wehn, Kees Goossens:
Exploiting expendable process-margins in DRAMs for run-time performance optimization. DATE 2014: 1-6 - [c13]Daniele Bortolotti, Andrea Bartolini, Christian Weis, Davide Rossi, Luca Benini:
Hybrid memory architecture for voltage scaling in ultra-low power multi-core biomedical processors. DATE 2014: 1-6 - [c12]MohammadSadegh Sadri, Matthias Jung, Christian Weis, Norbert Wehn, Luca Benini:
Energy optimization in 3D MPSoCs with Wide-I/O DRAM using temperature variation aware bank-wise refresh. DATE 2014: 1-4 - [c11]Matthias Jung, Christian Weis, Norbert Wehn, MohammadSadegh Sadri, Luca Benini:
Optimized active and power-down mode refresh control in 3D-DRAMs. VLSI-SoC 2014: 1-6 - 2013
- [j3]Veit Kleeberger, Christina Gimmler-Dumont, Christian Weis, Andreas Herkersdorf, Daniel Mueller-Gritschneder, Sani R. Nassif, Ulf Schlichtmann, Norbert Wehn:
A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience. IEEE Micro 33(4): 46-55 (2013) - [j2]Christian Weis, Igor Loi, Luca Benini, Norbert Wehn:
Exploration and Optimization of 3-D Integrated DRAM Subsystems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(4): 597-610 (2013) - [c10]Karthik Chandrasekar, Christian Weis, Benny Akesson, Norbert Wehn, Kees Goossens:
Towards variation-aware system-level power estimation of DRAMs: an empirical approach. DAC 2013: 23:1-23:8 - [c9]Karthik Chandrasekar, Christian Weis, Benny Akesson, Norbert Wehn, Kees Goossens:
System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs. DATE 2013: 236-241 - [c8]Matthias Jung, Christian Weis, Norbert Wehn, Karthik Chandrasekar:
TLM modelling of 3D stacked wide I/O DRAM subsystems: a virtual platform for memory controller design space exploration. RAPIDO 2013: 5:1-5:6 - 2012
- [j1]Philipp Schläfer, Christian Weis, Norbert Wehn, Matthias Alles:
Design Space of Flexible Multigigabit LDPC Decoders. VLSI Design 2012: 942893:1-942893:10 (2012) - [c7]Manil Dev Gomony, Christian Weis, Benny Akesson, Norbert Wehn, Kees Goossens:
DRAM selection and configuration for real-time mobile systems. DATE 2012: 51-56 - [c6]Christian Weis, Igor Loi, Luca Benini, Norbert Wehn:
An energy efficient DRAM subsystem for 3D integrated SoCs. DATE 2012: 1138-1141 - [c5]Christina Gimmler, Frank Kienle, Christian Weis, Norbert Wehn, Matthias Alles:
ASIC design of a Gbit/s LDPC decoder for iterative MIMO systems. ICNC 2012: 192-197 - [c4]Ivan Shcherbakov, Christian Weis, Norbert Wehn:
A High-Performance FPGA-Based Implementation of the LZSS Compression Algorithm. IPDPS Workshops 2012: 449-453 - [c3]Thomas Ilnseher, Frank Kienle, Christian Weis, Norbert Wehn:
A 2.15GBit/s turbo code decoder for LTE advanced base station applications. ISTC 2012: 21-25 - 2011
- [c2]Christian Weis, Norbert Wehn, Igor Loi, Luca Benini:
Design space exploration for 3D-stacked DRAMs. DATE 2011: 389-394 - [c1]Ivan Shcherbakov, Christian Weis, Norbert Wehn:
Bringing C++ productivity to VHDL world: From language definition to a case study. FDL 2011: 1-7
Coauthor Index
[c42] [c41] [j15] [j14] [j13] [c40] [i3] [c39] [c38] [c37] [c36] [i2] [j12] [c35] [c34] [c33] [c32] [c31] [c30] [i1] [j11] [j10] [j9] [j8] [c29] [c28] [c27] [c26] [j7] [c25] [c24] [c23] [c22] [c21] [c20] [j6] [j5] [c19] [c18] [c17] [c16] [c15] [j4] [c14] [c12] [c11] [j3] [j2] [c10] [c9] [c8] [j1] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
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