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Susumu Shuto
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2020 – today
- 2022
- [j6]Susumu Shuto
, Takashi Amemiya:
Sequential Bayesian inference for Weibull distribution parameters with initial hyperparameter optimization for system reliability estimation. Reliab. Eng. Syst. Saf. 224: 108516 (2022)
2010 – 2019
- 2011
- [j5]Daisaburo Takashima, Hidehiro Shiga
, Daisuke Hashimoto, Tadashi Miyakawa, Shinichiro Shiratake, Katsuhiko Hoya, Ryu Ogiwara, Ryosuke Takizawa, Ryosuke Doumae, Ryo Fukuda, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Susumu Shuto, Koji Yamakawa, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama:
A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs. IEEE J. Solid State Circuits 46(9): 2171-2179 (2011) - 2010
- [j4]Hidehiro Shiga
, Daisaburo Takashima, Shinichiro Shiratake, Katsuhiko Hoya, Tadashi Miyakawa, Ryu Ogiwara, Ryo Fukuda, Ryosuke Takizawa, Kosuke Hatsuda, Fumiyoshi Matsuoka, Yasushi Nagadomi, Daisuke Hashimoto, Hisaaki Nishimura
, Takeshi Hioka, Sumiko M. Doumae, Shoichi Shimizu, Mitsumo Kawano, Toyoki Taguchi, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Yoshinori Kumura, Yoshiro Shimojo, Yuki Yamada, Yoshihiro Minami, Susumu Shuto, Koji Yamakawa, Soichi Yamazaki, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama, Tohru Furuyama:
A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes. IEEE J. Solid State Circuits 45(1): 142-152 (2010) - [j3]Katsuhiko Hoya, Daisaburo Takashima, Shinichiro Shiratake, Ryu Ogiwara, Tadashi Miyakawa, Hidehiro Shiga
, Sumiko M. Doumae, Sumito Ohtsuki, Yoshinori Kumura, Susumu Shuto, Tohru Ozaki, Koji Yamakawa, Iwao Kunishima, Akihiro Nitayama, Shuso Fujii:
A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode. IEEE Trans. Very Large Scale Integr. Syst. 18(12): 1745-1752 (2010) - [c3]Daisaburo Takashima, Hidehiro Shiga
, Daisuke Hashimoto, Tadashi Miyakawa, Shinichiro Shiratake, Katsuhiko Hoya, Ryu Ogiwara, Ryosuke Takizawa, Ryosuke Doumae, Ryo Fukuda, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Susumu Shuto, Koji Yamakawa, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama:
A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAM. ISSCC 2010: 262-263
2000 – 2009
- 2009
- [c2]Hidehiro Shiga
, Daisaburo Takashima, Shinichiro Shiratake, Katsuhiko Hoya, Tadashi Miyakawa, Ryu Ogiwara, Ryo Fukuda, Ryosuke Takizawa, Kosuke Hatsuda, Fumiyoshi Matsuoka, Yasushi Nagadomi, Daisuke Hashimoto, Hisaaki Nishimura, Takeshi Hioka, Sumiko M. Doumae, Shoichi Shimizu, Mitsumo Kawano, Toyoki Taguchi, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Yoshinori Kumura, Yoshiro Shimojo, Yuki Yamada, Yoshihiro Minami, Susumu Shuto, Koji Yamakawa, Soichi Yamazaki, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama, Tohru Furuyama:
A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes. ISSCC 2009: 464-465 - 2006
- [c1]Katsuhiko Hoya, Daisaburo Takashima, Shinichiro Shiratake, Ryu Ogiwara, Tadashi Miyakawa, Hidehiro Shiga, Sumiko M. Doumae, Sumito Ohtsuki, Yoshinori Kumura, Susumu Shuto, Tohru Ozaki, Koji Yamakawa, Iwao Kunishima, Akihiro Nitayama, Shuso Fujii:
A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode. ISSCC 2006: 459-466 - 2000
- [j2]Ryu Ogiwara, Sumio Tanaka, Yasuo Itoh, Tadashi Miyakawa, Yoshiaki Takeuchi, Sumiko Mano Doumae, Hiroyuki Takenaka, Iwao Kunishima, Susumu Shuto, Osamu Hidaka, Sumito Ohtsuki, Shin'ichi Tanaka:
A 0.5-μm, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor. IEEE J. Solid State Circuits 35(4): 545-551 (2000)
1990 – 1999
- 1999
- [j1]Daisaburo Takashima, Susumu Shuto, Iwao Kunishima, Hiroyuki Takenaka, Yukihito Oowaki, Shin'ichi Tanaka:
A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive. IEEE J. Solid State Circuits 34(11): 1557-1563 (1999)
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