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Youssef Travaly
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2010 – 2019
- 2011
- [j2]Geert Van der Plas
, Paresh Limaye, Igor Loi, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Antonio Pullini, Federico Angiolini, Luca Benini
, Wim Dehaene, Youssef Travaly, Eric Beyne
, Paul Marchal:
Design Issues and Considerations for Low-Cost 3-D TSV IC Technology. IEEE J. Solid State Circuits 46(1): 293-307 (2011) - [c9]Yuuki Araga, Makoto Nagata
, Geert Van der Plas
, Jaemin Kim, Nikolaos Minas, Pol Marchal, Youssef Travaly, Michael Libois, Antonio La Manna, Wenqi Zhang, Eric Beyne
:
In-tier diagnosis of power domains in 3D TSV ICs. 3DIC 2011: 1-6 - 2010
- [j1]Y. Yang, Riet Labie, F. Ling, C. Zhao, A. Radisic, Jan Van Olmen, Youssef Travaly, Bert Verlinden, Ingrid De Wolf:
Processing assessment and adhesion evaluation of copper through-silicon vias (TSVs) for three-dimensional stacked-integrated circuit (3D-SIC) architectures. Microelectron. Reliab. 50(9-11): 1636-1640 (2010) - [c8]Yann Civale, Marcel Gonzalez, Deniz Sabuncuoglu Tezcan, Youssef Travaly, Philippe Soussan, Eric Beyne
:
A novel concept for ultra-low capacitance via-last TSV. 3DIC 2010: 1-4 - [c7]Anne Jourdain, Thibault Buisson, Alain Phommahaxay, Mark Privett, Dan Wallace, Sumant Sood, Peter Bisson, Eric Beyne
, Youssef Travaly, Bart Swinnen:
300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications. 3DIC 2010: 1-4 - [c6]Geert Van der Plas, Steven Thijs, Dimitri Linten, Guruprasad Katti, Paresh Limaye, Abdelkarim Mercha, Michele Stucchi, Herman Oprins, Bart Vandevelde, Nikolaos Minas, Miro Cupac, Morin Dehan, Marc Nelis, Rahul Agarwal, Wim Dehaene, Youssef Travaly, Eric Beyne
, Paul Marchal:
Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions. CICC 2010: 1-4 - [c5]Geert Van der Plas
, Paresh Limaye, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Domae Shinichi, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Wim Dehaene, Youssef Travaly, Pol Marchal, Eric Beyne
:
Design issues and considerations for low-cost 3D TSV IC technology. ISSCC 2010: 148-149
2000 – 2009
- 2009
- [c4]Ramakanth Alapati, Youssef Travaly, Jan Van Olmen, Ricardo Cotrin Teixeira
, Jan Vaes
, Marc van Cauwenbergh, Anne Jourdain, Greet Verbinnen, Gino Marcuccilli, Glenn Florence, Shay Wolfling, Christine Pelissier, Haiping Zhang, Jaydeep Sinha, Andreas Machura, Irfan Malik:
TSV metrology and inspection challenges. 3DIC 2009: 1-4 - [c3]Yann Civale, Deniz Sabuncuoglu Tezcan, Harold G. G. Philipsen
, P. Jaenen, Rahul Agarwal, F. Duval, Philippe Soussan, Youssef Travaly, Eric Beyne
:
Die stacking using 3D-wafer level packaging copper/polymer through-si via technology and Cu/Sn interconnect bumping. 3DIC 2009: 1-4 - [c2]Jan Van Olmen, Jan Coenen, Wim Dehaene, Kristin De Meyer, Cedric Huyghebaert, Anne Jourdain, Guruprasad Katti, Abdelkarim Mercha, Michal Rakowski, Michele Stucchi, Youssef Travaly, Eric Beyne
, Bart Swinnen:
3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV). 3DIC 2009: 1-5 - 2006
- [c1]Mandeep Bamal, Youssef Travaly, Wenqi Zhang, Michele Stucchi, Karen Maex:
Impact of interconnect resistance increase on system performance of low power and high performance designs. SLIP 2006: 85-90
Coauthor Index
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