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2010 – 2019
- 2011
[j4]Xiaoji Ye, Wei Dong, Peng Li, Sani R. Nassif:
Hierarchical Multialgorithm Parallel Circuit Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(1): 45-58 (2011)- 2010
- [j3]Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu:
Scalable Analysis of Mesh-Based Clock Distribution Networks Using Application-Specific Reduced Order Modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(9): 1342-1353 (2010) - [j2]Xiaoji Ye, Peng Li, Frank Ying Liu:
Exact Time-Domain Second-Order Adjoint-Sensitivity Computation for Linear Circuit Analysis and Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(1): 236-248 (2010) - [c13]Xiaoji Ye, Peng Li:
Parallel program performance modeling for runtime optimization of multi-algorithm circuit simulation. DAC 2010: 561-566 - [c12]Zhiyu Zeng, Xiaoji Ye, Zhuo Feng, Peng Li:
Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation. DAC 2010: 831-836 - [c11]Xiaoji Ye, Peng Li:
On-the-fly runtime adaptation for efficient execution of parallel multi-algorithm circuit simulation. ICCAD 2010: 298-304 - [c10]Venkata Rajesh Mekala, Yifang Liu, Xiaoji Ye, Jiang Hu, Peng Li:
Accurate clock mesh sizing via sequential quadraticprogramming. ISPD 2010: 135-142
2000 – 2009
- 2009
- [c9]Xiaoji Ye, Srinath Narasimhan, Peng Li:
Leveraging efficient parallel pattern search for clock mesh optimization. ICCAD 2009: 529-534 - [c8]Xiaoji Ye, Peng Li:
An application-specific adjoint sensitivity analysis framework for clock mesh sensitivity computation. ISQED 2009: 634-640 - 2008
- [c7]Wei Dong, Peng Li, Xiaoji Ye:
WavePipe: parallel transient simulation of analog and digital circuits on multi-core shared-memory machines. DAC 2008: 238-243 - [c6]Xiaoji Ye, Wei Dong, Peng Li, Sani R. Nassif:
MAPS: multi-algorithm parallel circuit simulation. ICCAD 2008: 73-78 - [c5]Xiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jiang Hu:
Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding. ISQED 2008: 627-632 - 2007
- [j1]Xiaoji Ye, Frank Liu, Peng Li:
Fast Variational Interconnect Delay and Slew Computation Using Quadratic Models. IEEE Trans. Very Large Scale Integr. Syst. 15(8): 913-926 (2007) - [c4]Wei Dong, Peng Li, Xiaoji Ye:
Efficient Frequency-Domain Simulation of Massive Clock Meshes Using Parallel Harmonic Balance. CICC 2007: 631-634 - [c3]Xiaoji Ye, Yaping Zhan, Peng Li:
Statistical Leakage Power Minimization Using Fast Equi-Slack Shell Based Optimization. DAC 2007: 853-858 - [c2]Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu:
Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding. ICCAD 2007: 627-631 - 2006
- [c1]Xiaoji Ye, Peng Li, Frank Liu:
Practical variation-aware interconnect delay and slew analysis for statistical timing verification. ICCAD 2006: 54-59
Coauthor Index
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