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Ruwan N. S. Ratnayake

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2000 – 2009

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2008
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Ruwan N. S. Ratnayake, Aleksandar Kavcic, Gu-Yeon Wei:
A High-Throughput Maximum a Posteriori Probability Detector. IEEE J. Solid State Circuits 43(8): 1846-1858 (2008)
2007
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Ruwan N. S. Ratnayake, Aleksandar Kavcic, Gu-Yeon Wei:
A High-Throughput Maximum a posteriori Probability Detector. CICC 2007: 455-458
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Ruwan N. S. Ratnayake, Erich F. Haratsch, Gu-Yeon Wei:
A Bit-Node Centric Architecture for Low-Density Parity-Check Decoders. GLOBECOM 2007: 265-270
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Ruwan N. S. Ratnayake, Erich F. Haratsch, Gu-Yeon Wei:
Serial Sum-Product Architecture for Low-Density Parity-Check Codes. ICCCN 2007: 154-158
2004
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Ruwan N. S. Ratnayake, Gu-Yeon Wei, Aleksandar Kavcic:
Pipelined parallel architecture for high throughput MAP detectors. ISCAS (2) 2004: 505-508

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