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ORCIDShih-Chieh Chang
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2020 – today
- 2025
[c115]Yu-Hsuan Chen, Yu-Chen Cheng, Yong-Fong Chang, Yu-Che Lee, Jia-Wei Lin, Hsun-Wei Pao, Peng-Wen Chen, Po-Yu Chen, Hao-Yun Chen, Yung-Chih Chen, Chun-Yao Wang, Shih-Chieh Chang:
Dynamic IR-Drop Prediction Through a Multi-Task U-Net with Package Effect Consideration. DATE 2025: 1-7- [c114]Kuan-Ling Chou
, Cheng-Lung Wang, Yung-Chih Chen, Wuqian Tang, Yi-Ting Li, Shih-Chieh Chang, Chun-Yao Wang:
CNN Model Optimization Using a Hybrid Approach of Genetic Algorithm-based Pruning and Retraining with Knowledge Distillation. ACM Great Lakes Symposium on VLSI 2025: 667-672 - [c113]Pin-Yuan Yang, Yu-Shan Deng, Chieh-Shan Lin, An-Chun Luo, Shih-Chieh Chang:
Coloring 3D Avatars with Single-Image. VISIGRAPP (2): VISAPP 2025: 903-910 - [i10]Yan-Cheng Guo, Tian-Sheuan Chang, Chih-Sheng Lin, Bo-Cheng Chiou, Chih-Ming Lai, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang:
CIMR-V: An End-to-End SRAM-based CIM Accelerator with RISC-V for AI Edge Device. CoRR abs/2503.22072 (2025) - 2024
- [j57]Ping-Chun Wu, Jian-Wei Su, Li-Yang Hong, Jin-Sheng Ren, Chih-Han Chien, Ho-Yu Chen, Chao-En Ke, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang:
A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips. IEEE J. Solid State Circuits 59(1): 196-207 (2024) - [j56]Ping-Chun Wu, Jian-Wei Su, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Ho-Yu Chen, Chen-Hsun Lin, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chih-I Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang:
An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips. IEEE J. Solid State Circuits 59(7): 2297-2309 (2024) - [j55]Jian-Wei Su, Pei-Jung Lu, Ping-Chun Wu, Yen-Chi Chou, Ta-Wei Liu, Yen-Lin Chung, Li-Yang Hung, Jin-Sheng Ren, Wei-Hsing Huang, Chih-Han Chien, Peng-I Mei, Sih-Han Li, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Hao-Chiao Hong, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang:
8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 2304-2308 (2024) - [c112]Wuqian Tang, Yi-Ting Li, Kai-Po Hsu, Kuan-Ling Chou, You-Cheng Lin, Chia-Feng Chien, Tzu-Li Hsu, Yung-Chih Chen, Ting-Chi Wang, Shih-Chieh Chang, TingTing Hwang, Chun-Yao Wang:
A Hybrid Approach to Reverse Engineering on Combinational Circuits. DATE 2024: 1-2 - [c111]Yong-Fong Chang, Yung-Chih Chen, Yu-Chen Cheng, Shu-Hong Lin, Che-Hsu Lin, Chun-Yuan Chen, Yu-Hsuan Chen, Yu-Che Lee, Jia-Wei Lin, Hsun-Wei Pao, Shih-Chieh Chang, Yi-Ting Li, Chun-Yao Wang:
IR drop Prediction Based on Machine Learning and Pattern Reduction. ACM Great Lakes Symposium on VLSI 2024: 516-519 - [c110]Yan-Cheng Guo, Tian-Sheuan Chang, Chih-Sheng Lin, Bo-Cheng Chiou, Chih-Ming Lai, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang:
CIMR-V: An End-to-End SRAM-based CIM Accelerator with RISC-V for AI Edge Device. ISCAS 2024: 1-5 - [c109]Wuqian Tang, Chuan-Shun Huang, Yung-Chih Chen, Yi-Ting Li, Shih-Chieh Chang, Chun-Yao Wang:
Model Reduction Using a Hybrid Approach of Genetic Algorithm and Rule-based Method. SOCC 2024: 1-6 - [c108]Chih-Sheng Lin, Bo-Cheng Chiou, Yin-Jia Yang, Jian-Wei Su, Kuo-Hua Tseng, Yun-Ting Ho, Chih-Ming Lai, Sih-Han Li, Tian-Sheuan Chang, Shan-Ming Chang, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Tuo-Hung Hou:
Empowering Local Differential Privacy: A 5718 TOPS/W Analog PUF-Based In-Memory Encryption Macro for Dynamic Edge Security. VLSI Technology and Circuits 2024: 1-2 - [c107]Wei Lu, Jie Zhang, Yi-Hui Wei, Hsu-Ming Hsiao, Sih-Han Li, Chao-Kai Hsu, Chih-Cheng Hsiao, Feng-Hsiang Lo, Shyh-Shyuan Sheu, Chin-Hung Wang, Wei-Chung Lo, Shih-Chieh Chang, Hung-Ming Chen, Kuan-Neng Chen, Po-Tsang Huang:
Scalable Embedded Multi-Die Active Bridge (S-EMAB) Chips with Integrated LDOs for Low-Cost Programmable 2.5D/3.5D Packaging Technology. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j54]Jian-Wei Su, Yen-Chi Chou, Ruhui Liu, Ta-Wei Liu, Pei-Jung Lu, Ping-Chun Wu, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Tianlong Pan, Chuan-Jia Jhang, Wei-Hsing Huang, Chih-Han Chien, Peng-I Mei, Sih-Han Li, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chih-I Wu, Xin Si, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang:
A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips. IEEE J. Solid State Circuits 58(3): 877-892 (2023) - [j53]Tay-Jyi Lin, Yi-Hsuan Ting, Meng-Ze Hsu, Kuan-Han Lin, Chung-Ming Huang, Fu-Cheng Tsai, Shyh-Shyuan Sheu, Shih-Chieh Chang, Chingwei Yeh, Jinn-Shyan Wang:
A 16 nm 140 TOPS/W 5 μJ/Inference Keyword Spotting Engine Based on 1D-BCNN. IEEE Trans. Circuits Syst. II Express Briefs 70(12): 4564-4568 (2023) - [c106]Jian-Jia Huang, Shih-Chieh Chang, Cheng-Hsu Cheng, Timothy Wan, Yu-Cheng Pei:
Gait Analysis in Powered Exoskeleton-Assisted Walking in Patients with Stroke: A Case Series Cohort. APSIPA ASC 2023: 187-194 - [c105]Chih-Tsun Huang, Juin-Ming Lu, Yao-Hua Chen, Ming-Chih Tung, Shih-Chieh Chang:
Optimization of AI SoC with Compiler-assisted Virtual Design Platform. ISPD 2023: 187-193 - [c104]Ping-Chun Wu, Jian-Wei Su, Li-Yang Hong, Jin-Sheng Ren, Chih-Han Chien, Ho-Yu Chen, Chao-En Ke, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang:
A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices. ISSCC 2023: 126-127 - [c103]Ming-Hung Wu, Ming-Chun Hong, Ching Shih, Yao-Jen Chang, Yu-Chen Hsin, Shih-Ching Chiu, Kuan-Ming Chen, Yi-Hui Su, Chih-Yao Wang, Shan-Yi Yang, Guan-Long Chen, Hsin-Han Lee, Sk. Ziaur Rahaman, I-Jung Wang, Chen-Yi Shih, Tsun-Chun Chang, Jeng-Hua Wei, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Tuo-Hung Hou:
U-MRAM: Transistor-Less, High-Speed (10 ns), Low-Voltage (0.6 V), Field-Free Unipolar MRAM for High-Density Data Memory. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c102]Zong-Han Lee, Fu-Cheng Tsai, Shih-Chieh Chang:
Robust Binary Neural Network against Noisy Analog Computation. DATE 2022: 484-489 - [c101]Ping-Chun Wu, Jian-Wei Su, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Ho-Yu Chen, Chen-Hsun Lin, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Chih-I Wu, Meng-Fan Chang:
A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices. ISSCC 2022: 1-3 - 2021
- [j52]Yi-Wen Hung, Yung-Chih Chen, Chi Lo, Austin Go So, Shih-Chieh Chang:
Dynamic Workload Allocation for Edge Computing. IEEE Trans. Very Large Scale Integr. Syst. 29(3): 519-529 (2021) - [c100]Chih-Sheng Lin, Fu-Cheng Tsai, Jian-Wei Su, Sih-Han Li, Tian-Sheuan Chang, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Chih-I Wu, Tuo-Hung Hou:
A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration. A-SSCC 2021: 1-3 - [c99]Jian-Wei Su, Yen-Chi Chou, Ruhui Liu, Ta-Wei Liu, Pei-Jung Lu, Ping-Chun Wu, Yen-Lin Chung, Li-Yang Hung, Jin-Sheng Ren, Tianlong Pan, Sih-Han Li, Shih-Chieh Chang, Shyh-Shyuan Sheu, Wei-Chung Lo, Chih-I Wu, Xin Si, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang:
16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips. ISSCC 2021: 250-252 - 2020
- [c98]Chu-Chien Wei, Li-Huang Tsai, Hsin-Ping Chou, Shih-Chieh Chang:
Person Identification by Walking Gesture Using Skeleton Sequences. ACIVS 2020: 205-214 - [c97]Xiang-Xiu Wu, Yi-Wen Hung, Yung-Chih Chen, Shih-Chieh Chang:
Accuracy Tolerant Neural Networks Under Aggressive Power Optimization. DATE 2020: 774-779 - [c96]Hsin-Ping Chou, Shih-Chieh Chang, Jia-Yu Pan, Wei Wei, Da-Cheng Juan:
Remix: Rebalanced Mixup. ECCV Workshops (6) 2020: 95-110 - [c95]Chieh-Yang Chen, Pei-Hsin Wang, Shih-Chieh Chang, Da-Cheng Juan, Wei Wei, Jia-Yu Pan:
AirConcierge: Generating Task-Oriented Dialogue via Efficient Large-Scale Knowledge Retrieval. EMNLP (Findings) 2020: 884-897 - [c94]Jian-Wei Su, Xin Si, Yen-Chi Chou, Ting-Wei Chang, Wei-Hsing Huang, Yung-Ning Tu, Ruhui Liu, Pei-Jung Lu, Ta-Wei Liu, Jing-Hong Wang, Zhixiao Zhang, Hongwu Jiang, Shanshi Huang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shyh-Shyuan Sheu, Sih-Han Li, Heng-Yuan Lee, Shih-Chieh Chang, Shimeng Yu, Meng-Fan Chang:
15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips. ISSCC 2020: 240-242 - [i9]Li-Huang Tsai, Shih-Chieh Chang, Yu-Ting Chen, Jia-Yu Pan, Wei Wei, Da-Cheng Juan:
Calibrated BatchNorm: Improving Robustness Against Noisy Weights in Neural Networks. CoRR abs/2007.03230 (2020) - [i8]Hsin-Ping Chou, Shih-Chieh Chang, Jia-Yu Pan, Wei Wei, Da-Cheng Juan:
Remix: Rebalanced Mixup. CoRR abs/2007.03943 (2020) - [i7]Pei-Hsin Wang, Sheng-Iou Hsieh, Shih-Chieh Chang, Yu-Ting Chen, Jia-Yu Pan, Wei Wei, Da-Chang Juan:
Contextual Temperature for Language Modeling. CoRR abs/2012.13575 (2020)
2010 – 2019
- 2019
- [c93]Yun-Ting Wang, Kai-Chiang Wu, Chung-Han Chou, Shih-Chieh Chang:
Aging-aware chip health prediction adopting an innovative monitoring strategy. ASP-DAC 2019: 179-184 - [c92]Hao-Yun Chen, Jhao-Hong Liang, Shih-Chieh Chang, Jia-Yu Pan, Yu-Ting Chen, Wei Wei, Da-Cheng Juan:
Improving Adversarial Robustness via Guided Complement Entropy. ICCV 2019: 4880-4888 - [c91]Hao-Yun Chen, Pei-Hsin Wang, Chun-Hao Liu, Shih-Chieh Chang, Jia-Yu Pan, Yu-Ting Chen, Wei Wei, Da-Cheng Juan:
Complement Objective Training. ICLR (Poster) 2019 - [c90]Chun-Hao Liu, Da-Cheng Juan, Xuan-An Tseng, Wei Wei, Yu-Ting Chen, Jia-Yu Pan, Shih-Chieh Chang:
Hierarchical LSTM: Modeling Temporal Dynamics and Taxonomy in Location-Based Mobile Check-Ins. PAKDD (2) 2019: 217-228 - [i6]Hao-Yun Chen, Pei-Hsin Wang, Chun-Hao Liu, Shih-Chieh Chang, Jia-Yu Pan, Yu-Ting Chen, Wei Wei, Da-Cheng Juan:
Complement Objective Training. CoRR abs/1903.01182 (2019) - [i5]Hao-Yun Chen, Jhao-Hong Liang, Shih-Chieh Chang, Jia-Yu Pan, Yu-Ting Chen, Wei Wei, Da-Cheng Juan:
Improving Adversarial Robustness via Guided Complement Entropy. CoRR abs/1903.09799 (2019) - [i4]Hao-Yun Chen, Li-Huang Tsai, Shih-Chieh Chang, Jia-Yu Pan, Yu-Ting Chen, Wei Wei, Da-Cheng Juan:
Learning with Hierarchical Complement Objective. CoRR abs/1911.07257 (2019) - 2018
- [j51]Chung-Han Chou, Tsui-Yun Chang, Kai-Chiang Wu, Shih-Chieh Chang:
Sensor-Based Time Speculation in the Presence of Timing Variability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1133-1142 (2018) - [j50]Kai-Hsiang Hsu, Yung-Chih Chen, You-Luen Lee, Shih-Chieh Chang:
Contactless Testing for Prebond Interposers. IEEE Trans. Very Large Scale Integr. Syst. 26(6): 1005-1014 (2018) - [j49]Cheng-Hung Lin, Sze-Chen Cho, Shih-Chieh Chang:
An Adaptive Mechanism for Designing Efficient Snoop Filters. IEEE Trans. Very Large Scale Integr. Syst. 26(7): 1233-1240 (2018) - [c89]An-Chieh Cheng, Jin-Dong Dong, Chi-Hung Hsu, Shu-Huan Chang, Min Sun, Shih-Chieh Chang, Jia-Yu Pan, Yu-Ting Chen, Wei Wei, Da-Cheng Juan:
Searching toward pareto-optimal device-aware neural architectures. ICCAD 2018: 136 - [i3]Chi-Hung Hsu, Shu-Huan Chang, Da-Cheng Juan, Jia-Yu Pan, Yu-Ting Chen, Wei Wei, Shih-Chieh Chang:
MONAS: Multi-Objective Neural Architecture Search using Reinforcement Learning. CoRR abs/1806.10332 (2018) - [i2]An-Chieh Cheng, Jin-Dong Dong, Chi-Hung Hsu, Shu-Huan Chang, Min Sun, Shih-Chieh Chang, Jia-Yu Pan, Yu-Ting Chen, Wei Wei, Da-Cheng Juan:
Searching Toward Pareto-Optimal Device-Aware Neural Architectures. CoRR abs/1808.09830 (2018) - 2017
- [j48]Chung-Han Chou, Yenting Lai, Yi-Chun Chang, Chih-Yu Wang, Liang-Chia Cheng, Shih-Hsu Huang, Shih-Chieh Chang:
Ping-Pong Mesh: A New Resonant Clock Design for Surge Current and Area Overhead Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(1): 146-155 (2017) - [j47]Yin-Chi Peng, Chien-Chih Chen, Hsiang-Jen Tsai, Keng-Hao Yang, Pei-Zhe Huang, Shih-Chieh Chang, Wen-Ben Jone, Tien-Fu Chen:
Leak Stopper: An Actively Revitalized Snoop Filter Architecture with Effective Generation Control. ACM Trans. Design Autom. Electr. Syst. 22(3): 46:1-46:27 (2017) - [j46]Cheng-Hung Lin, Jin-Cheng Li, Chen-Hsiung Liu, Shih-Chieh Chang:
Perfect Hashing Based Parallel Algorithms for Multiple String Matching on Graphic Processing Units. IEEE Trans. Parallel Distributed Syst. 28(9): 2639-2650 (2017) - [j45]Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark M. Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson:
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 1-20 (2017) - [c88]Yu-Guang Chen, Michihiro Shintani, Takashi Sato, Yiyu Shi, Shih-Chieh Chang:
Pattern based runtime voltage emergency prediction: An instruction-aware block sparse compressed sensing approach. ASP-DAC 2017: 543-548 - [c87]Kassan Unda, Chung-Han Chou, Shih-Chieh Chang, Cheng Zhuo, Yiyu Shi:
CN-SIM: A cycle-accurate full system power delivery noise simulator. ASP-DAC 2017: 554-559 - [c86]Chi Lo, Yu-Yi Su, Chun-Yi Lee, Shih-Chieh Chang:
A Dynamic Deep Neural Network Design for Efficient Workload Allocation in Edge Computing. ICCD 2017: 273-280 - [c85]You-Luen Lee, Da-Cheng Juan, Xuan-An Tseng, Yu-Ting Chen, Shih-Chieh Chang:
DC-Prophet: Predicting Catastrophic Machine Failures in DataCenters. ECML/PKDD (3) 2017: 64-76 - [i1]You-Luen Lee, Da-Cheng Juan, Xuan-An Tseng, Yu-Ting Chen, Shih-Chieh Chang:
DC-Prophet: Predicting Catastrophic Machine Failures in DataCenters. CoRR abs/1709.06537 (2017) - 2016
- [j44]Hsuan-Ming Chou, Yi-Chiao Chen, Keng-Hao Yang, Jean Tsao, Shih-Chieh Chang, Wen-Ben Jone, Tien-Fu Chen:
High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 1169-1173 (2016) - [j43]Chung-Han Chou, Hua-Hsin Yeh, Shih-Hsu Huang, Yow-Tyng Nieh, Shih-Chieh Chang, Yung-Tai Chang:
Skew Minimization With Low Power for Wide-Voltage-Range Multipower-Mode Designs. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 1189-1192 (2016) - [c84]Yu-Guang Chen, Wan-Yu Wen, Yun-Ting Wang, You-Luen Lee, Shih-Chieh Chang:
A novel low-cost dynamic logic reconfigurable structure strategy for low power optimization. ASP-DAC 2016: 250-255 - [c83]Travis E. Schulze, Kevin A. Kwiat, Charles A. Kamhoua, Shih-Chieh Chang, Yiyu Shi:
RECORD: Temporarily Randomized Encoding of COmbinational Logic for Resistance to Data Leakage from hardware Trojan. AsianHOST 2016: 1-6 - [c82]Yi-Hsuan Ting, Chih-Yang Wang, Yu-Sian Chang, Tay-Jyi Lin, Shih-Chieh Chang, Jinn-Shyan Wang:
Overoptimistic voltage scaling in pre-error AVS systems and learning-based alleviation. SoCC 2016: 350-355 - 2015
- [j42]Ping-Huang Tsai, Shih-Chieh Chang, Fang-Chun Liu, Jen-Ho Tsao, Yung-Hung Wang, Men-Tzung Lo:
A Novel Application of Multiscale Entropy in Electroencephalography to Predict the Efficacy of Acetylcholinesterase Inhibitor in Alzheimer's Disease. Comput. Math. Methods Medicine 2015: 953868:1-953868:8 (2015) - [j41]Boris Thies, Alexander Groos, Martin Schulz, Ching-Feng Li, Shih-Chieh Chang, Jörg Bendix:
Frequency of Low Clouds in Taiwan Retrieved from MODIS Data and Its Relation to Cloud Forest Occurrence. Remote. Sens. 7(10): 12986-13004 (2015) - [j40]Yu-Guang Chen, Wan-Yu Wen, Yiyu Shi, Wing-Kai Hon, Shih-Chieh Chang:
Novel Spare TSV Deployment for 3-D ICs Considering Yield and Timing Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(4): 577-588 (2015) - [j39]Mac Y. C. Kao, Kun-Ting Tsai, Shih-Chieh Chang:
A Fault Detection and Tolerance Architecture for Post-Silicon Skew Tuning. IEEE Trans. Very Large Scale Integr. Syst. 23(7): 1210-1220 (2015) - [j38]Hsuan-Ming Chou, Ming-Yi Hsiao, Yi-Chiao Chen, Keng-Hao Yang, Jean Tsao, Chiao-Ling Lung, Shih-Chieh Chang, Wen-Ben Jone, Tien-Fu Chen:
Soft-Error-Tolerant Design Methodology for Balancing Performance, Power, and Reliability. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1628-1639 (2015) - [c81]Hsuan-Ming Chou, Hong-Chang Wu, Yi-Chiao Chen, Jean Tsao, Shih-Chieh Chang:
Hybrid coverage assertions for efficient coverage analysis across simulation and emulation environments. ASP-DAC 2015: 594-599 - [c80]Yu-Guang Chen, Wan-Yu Wen, Tao Wang, Yiyu Shi, Shih-Chieh Chang:
Q-Learning Based Dynamic Voltage Scaling for Designs with Graceful Degradation. ISPD 2015: 41-48 - 2014
- [j37]Yu-Guang Chen, Hui Geng, Kuan-Yu Lai, Yiyu Shi, Shih-Chieh Chang:
Multibit Retention Registers for Power Gated Designs: Concept, Design, and Deployment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(4): 507-518 (2014) - [j36]Cody Hao Yu, Chiao-Ling Lung, Yi-Lun Ho, Ruei-Siang Hsu, Ding-Ming Kwai, Shih-Chieh Chang:
Thermal-Aware On-Line Scheduler for 3-D Many-Core Processor Throughput Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(5): 763-773 (2014) - [j35]Wan-Yu Wen, Jin-Cheng Li, Sheng-Yuan Lin, Jing-Yi Chen, Shih-Chieh Chang:
A Fuzzy-Matching Model With Grid Reduction for Lithography Hotspot Detection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(11): 1671-1680 (2014) - [c79]Jui-Hung Chien, Ruei-Siang Hsu, Hsueh-Ju Lin, Ka-Yi Yeh, Shih-Chieh Chang:
Contactless Stacked-die Testing for Pre-bond Interposers. DAC 2014: 8:1-8:6 - [c78]Yu-Guang Chen, Tao Wang, Kuan-Yu Lai, Wan-Yu Wen, Yiyu Shi, Shih-Chieh Chang:
Critical Path Monitor Enabled Dynamic Voltage Scaling for Graceful Degradation in Sub-Threshold Designs. DAC 2014: 98:1-98:6 - [c77]Yu-Guang Chen, Kuan-Yu Lai, Ming-Chao Lee, Yiyu Shi, Wing-Kai Hon, Shih-Chieh Chang:
Yield and timing constrained spare TSV assignment for three-dimensional integrated circuits. DATE 2014: 1-4 - [c76]Jui-Hung Chien, Hao Yu, Ruei-Siang Hsu, Hsueh-Ju Lin, Shih-Chieh Chang:
Package geometric aware thermal analysis by infrared-radiation thermal images. DATE 2014: 1-4 - [c75]Hsuan-Ming Chou, Hong-Chang Wu, Yi-Chiao Chen, Shih-Chieh Chang:
Concurrency-oriented SoC re-certification by reusing block-level test vectors. ISQED 2014: 140-147 - 2013
- [j34]Wen-Tsuen Chen, Youn-Long Lin, Chen-Yi Lee, Jeng-Long Chiang, Meng-Fan Chang, Shih-Chieh Chang:
Strengthening Modern Electronics Industry Through the National Program for Intelligent Electronics in Taiwan. IEEE Access 1: 123-130 (2013) - [j33]Cheng-Hung Lin, Chen-Hsiung Liu, Lung-Sheng Chien, Shih-Chieh Chang:
Accelerating Pattern Matching Using a Novel Parallel Algorithm on GPUs. IEEE Trans. Computers 62(10): 1906-1916 (2013) - [j32]Chiao-Ling Lung, Yu-Shih Su, Hsih-Hsiu Huang, Yiyu Shi, Shih-Chieh Chang:
Through-Silicon Via Fault-Tolerant Clock Networks for 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(7): 1100-1109 (2013) - [j31]Jinn-Shyan Wang, Keng-Jui Chang, Chingwei Yeh, Shih-Chieh Chang:
Embedding Repeaters in Silicon IPs for Cross-IP Interconnections. IEEE Trans. Very Large Scale Integr. Syst. 21(3): 597-601 (2013) - [c74]Sheng-Yuan Lin, Jing-Yi Chen, Jin-Cheng Li, Wan-Yu Wen, Shih-Chieh Chang:
A novel fuzzy matching model for lithography hotspot detection. DAC 2013: 68:1-68:6 - [c73]Wen-Pin Tu, Chung-Han Chou, Shih-Hsu Huang, Shih-Chieh Chang, Yow-Tyng Nieh, Chien-Yung Chou:
Low-power timing closure methodology for ultra-low voltage designs. ICCAD 2013: 697-704 - [c72]Chung-Han Chou, Nien-Yu Tsai, Hao Yu, Yiyu Shi, Jui-Hung Chien, Shih-Chieh Chang:
On the futility of thermal through-silicon-vias. VLSI-DAT 2013: 1-6 - 2012
- [j30]Ming-Chao Lee, Yiyu Shi, Shih-Chieh Chang:
Efficient Wakeup Scheduling Considering Both Resource Usage and Timing Budget for Power Gating Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(7): 1041-1049 (2012) - [j29]Shih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang:
Timing Optimization in Sequential Circuit by Exploiting Clock-Gating Logic. ACM Trans. Design Autom. Electr. Syst. 17(2): 16:1-16:15 (2012) - [c71]Mac Y. C. Kao, Kun-Ting Tsai, Hsuan-Ming Chou, Shih-Chieh Chang:
Post silicon skew tuning: Survey and analysis. ASP-DAC 2012: 646-651 - [c70]Hsiu-Yi Lin, Chun-Yao Wang, Shih-Chieh Chang, Yung-Chih Chen, Hsuan-Ming Chou, Ching-Yi Huang, Yen-Chi Yang, Chun-Chien Shen:
A probabilistic analysis method for functional qualification under Mutation Analysis. DATE 2012: 147-152 - [c69]Kai-Chiang Wu, Ming-Chao Lee, Diana Marculescu, Shih-Chieh Chang:
Mitigating lifetime underestimation: A system-level approach considering temperature variations and correlations between failure mechanisms. DATE 2012: 1269-1274 - [c68]Yu-Guang Chen, Yiyu Shi, Kuan-Yu Lai, Hui Geng, Shih-Chieh Chang:
Efficient multiple-bit retention register assignment for power gated design: Concept and algorithms. ICCAD 2012: 309-316 - [c67]Cheng-Hung Lin, Chen-Hsiung Liu, Shih-Chieh Chang, Wing-Kai Hon:
Memory-efficient pattern matching architectures using perfect hashing on graphic processing units. INFOCOM 2012: 1978-1986 - [c66]Ming-Chao Lee, Yiyu Shi, Yu-Guang Chen, Diana Marculescu, Shih-Chieh Chang:
Efficient on-line module-level wake-up scheduling for high performance multi-module designs. ISPD 2012: 97-104 - 2011
- [j28]Cheng-Hung Lin, Shih-Chieh Chang:
Efficient Pattern Matching Algorithm for Memory Architecture. IEEE Trans. Very Large Scale Integr. Syst. 19(1): 33-41 (2011) - [j27]Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska:
Performance Optimization Using Variable-Latency Design Style. IEEE Trans. Very Large Scale Integr. Syst. 19(10): 1874-1883 (2011) - [c65]Ming-Chao Lee, Yu-Guang Chen, Ding-Kei Huang, Shih-Chieh Chang:
NBTI-aware power gating design. ASP-DAC 2011: 609-614 - [c64]Chiao-Ling Lung, Yu-Shih Su, Shih-Hsiu Huang, Yiyu Shi, Shih-Chieh Chang:
Fault-tolerant 3D clock network. DAC 2011: 645-651 - [c63]Chiao-Ling Lung, Yi-Lun Ho, Ding-Ming Kwai, Shih-Chieh Chang:
Thermal-aware on-line task allocation for 3D multi-core processor throughput optimization. DATE 2011: 8-13 - [c62]Cheng-Hung Lin, Chen-Hsiung Liu, Shih-Chieh Chang:
Accelerating Regular Expression Matching Using Hierarchical Parallel Machines on GPU. GLOBECOM 2011: 1-5 - [c61]Chung-Han Chou, Nien-Yu Tsai, Hao Yu, Che-Rung Lee, Yiyu Shi, Shih-Chieh Chang:
On the preconditioner of conjugate gradient method - A power grid simulation perspective. ICCAD 2011: 494-497 - [c60]Hsuan-Ming Chou, Hao Yu, Shih-Chieh Chang:
Useful-skew clock optimization for multi-power mode designs. ICCAD 2011: 647-650 - [c59]Mac Y. C. Kao, Kun-Ting Tsai, Shih-Chieh Chang:
A robust architecture for post-silicon skew tuning. ICCAD 2011: 774-778 - [c58]Kai-Chiang Wu, Diana Marculescu, Ming-Chao Lee, Shih-Chieh Chang:
Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits. ISLPED 2011: 139-144 - [c57]Chiao-Ling Lung, Jui-Hung Chien, Yiyu Shi, Shih-Chieh Chang:
TSV fault-tolerant mechanisms with application to 3D clock networks. ISOCC 2011: 127-130 - 2010
- [j26]Kuo-Chih Liao, Shih-Chieh Chang, Cheng-Yang Chiu, Yu-Hsiang Chou:
Acute Response in vivo of a Fiber-Optic Sensor for Continuous Glucose Monitoring from Canine Studies on Point Accuracy. Sensors 10(8): 7789-7802 (2010) - [j25]De-Shiuan Chiou, Yu-Ting Chen, Da-Cheng Juan, Shih-Chieh Chang:
Sleep Transistor Sizing for Leakage Power Minimization Considering Temporal Correlation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(8): 1285-1289 (2010) - [j24]Yu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang, Shih-Chieh Chang, Yeong-Jar Chang:
Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(12): 1921-1930 (2010) - [j23]Da-Cheng Juan, Yu-Ting Chen, Ming-Chao Lee, Shih-Chieh Chang:
An Efficient Wake-Up Strategy Considering Spurious Glitches Phenomenon for Power Gating Designs. IEEE Trans. Very Large Scale Integr. Syst. 18(2): 246-255 (2010) - [c56]Yu-Chien Kao, Hsuan-Ming Chou, Kun-Ting Tsai, Shih-Chieh Chang:
An efficient phase detector connection structure for the skew synchronization system. DAC 2010: 729-734 - [c55]Chiao-Ling Lung, Zi-Yi Zeng, Chung-Han Chou, Shih-Chieh Chang:
Clock skew optimization considering complicated power modes. DATE 2010: 1474-1479 - [c54]Cheng-Hung Lin, Sheng-Yu Tsai, Chen-Hsiung Liu, Shih-Chieh Chang, Jyuo-Min Shyu:
Accelerating String Matching Using Multi-Threaded Algorithm on GPU. GLOBECOM 2010: 1-5 - [c53]Yu-Chien Kao, Hsuan-Ming Chou, Kun-Ting Tsai, Shih-Chieh Chang:
Synthesis of an efficient controlling structure for post-silicon clock skew minimization. ICCAD 2010: 746-749
2000 – 2009
- 2009
- [j22]Yu-Min Kuo, Yue-Lung Chang, Shih-Chieh Chang:
Efficient Boolean Characteristic Function for Timed Automatic Test Pattern Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(3): 417-425 (2009) - [j21]Yu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgorzata Marek-Sadowska:
Spare Cells With Constant Insertion for Engineering Change. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(3): 456-460 (2009) - [j20]De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang:
Sleep Transistor Sizing for Leakage Power Minimization Considering Charge Balancing. IEEE Trans. Very Large Scale Integr. Syst. 17(9): 1330-1334 (2009) - [c52]Ming-Chao Lee, Yu-Ting Chen, Yo-Tzu Cheng, Shih-Chieh Chang:
An efficient wakeup scheduling considering resource constraint for sensor-based power gating designs. ICCAD 2009: 457-460 - [c51]Yu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang, Shih-Chieh Chang, Yeong-Jar Chang:
Value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs. ICCAD 2009: 535-538 - 2008
- [j19]Yu-Shih Su, Po-Hsien Chang, Shih-Chieh Chang, TingTing Hwang:
Synthesis of a novel timing-error detection architecture. ACM Trans. Design Autom. Electr. Syst. 13(1): 14:1-14:14 (2008) - [c50]Cheng-Tao Hsieh, Jason Cong, Zhiru Zhang, Shih-Chieh Chang:
Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA. ASP-DAC 2008: 10-15 - [c49]Yu-Min Kuo, Shih-Hung Weng, Shih-Chieh Chang:
A novel sequential circuit optimization with clock gating logic. ICCAD 2008: 230-233 - [c48]Shih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang, Malgorzata Marek-Sadowska:
Timing analysis considering IR drop waveforms in power gating designs. ICCD 2008: 532-537 - 2007
- [j18]Cheng-Hung Lin, Chih-Tsun Huang, Chang-Ping Jiang, Shih-Chieh Chang:
Optimization of Pattern Matching Circuits for Regular Expression on FPGA. IEEE Trans. Very Large Scale Integr. Syst. 15(12): 1303-1310 (2007) - [c47]Cheng-Hung Lin, Yu-Tang Tai, Shih-Chieh Chang:
Optimization of pattern matching algorithm for memory based architecture. ANCS 2007: 11-16 - [c46]De-Shiuan Chiou, Da-Cheng Juan, Yu-Ting Chen, Shih-Chieh Chang:
Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization. DAC 2007: 81-86 - [c45]Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska:
An Efficient Mechanism for Performance Optimization of Variable-Latency Designs. DAC 2007: 976-981 - [c44]Yu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgorzata Marek-Sadowska:
Engineering change using spare cells with constant insertion. ICCAD 2007: 544-547 - [c43]Yu-Ting Chen, Da-Cheng Juan, Ming-Chao Lee, Shih-Chieh Chang:
An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon. ICCAD 2007: 779-782 - [c42]Aida Todri, Malgorzata Marek-Sadowska, Shih-Chieh Chang:
Analysis and optimization of power-gated ICs with multiple power gating configurations. ICCAD 2007: 783-790 - [c41]Aida Todri, Shih-Chieh Chang, Malgorzata Marek-Sadowska:
Electromigration and voltage drop aware power grid optimization for power gated ICs. ISLPED 2007: 391-394 - [c40]Yu-Min Kuo, Cheng-Hung Lin, Chun-Yao Wang, Shih-Chieh Chang, Pei-Hsin Ho:
Intelligent Random Vector Generator Based on Probability Analysis of Circuit Structure. ISQED 2007: 344-349 - [c39]Cheng-Tao Hsieh, Jian-Cheng Lin, Shih-Chieh Chang:
Efficient Transition-Mode Boolean Characteristic Function with Its Application to Maximum Instantaneous Current Analysis. ISQED 2007: 602-606 - 2006
- [j17]C.-T. Hsieh, J.-C. Lin, Shih-Chieh Chang:
Vectorless Estimation of Maximum Instantaneous Current for Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2341-2352 (2006) - [j16]Zhong-Zhen Wu, Shih-Chieh Chang:
Multiple wire reconnections based on implication flow graph. ACM Trans. Design Autom. Electr. Syst. 11(4): 939-952 (2006) - [j15]Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh:
Power minimization for dynamic PLAs. IEEE Trans. Very Large Scale Integr. Syst. 14(6): 616-624 (2006) - [c38]Kai-Chiang Wu, Cheng-Tao Hsieh, Shih-Chieh Chang:
Delay variation tolerance for domino circuits. ASP-DAC 2006: 354-359 - [c37]De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang, Chingwei Yeh:
Timing driven power gating. DAC 2006: 121-124 - [c36]Cheng-Hung Lin, Chih-Tsun Huang, Chang-Ping Jiang, Shih-Chieh Chang:
Optimization of regular expression pattern matching circuits on FPGA. DATE Designers' Forum 2006: 12-17 - [c35]Yu-Min Kuo, Yue-Lung Chang, Shih-Chieh Chang:
Efficient Boolean characteristic function for fast timed ATPG. ICCAD 2006: 96-99 - [c34]Yi-Le Huang, Chun-Yao Wang, Richard Yeh, Shih-Chieh Chang, Yung-Chih Chen:
Language-Based High Level Transaction Extraction on On-chip Buses. ISQED 2006: 231-236 - 2005
- [c33]Yen-Fong Lee, Shi-Yu Huang, Sheng-Yu Hsu, I-Ling Chen, Cheng-Tao Shieh, Jian-Cheng Lin, Shih-Chieh Chang:
Power estimation starategies for a low-power security processor. ASP-DAC 2005: 367-371 - [c32]Cheng-Hung Lin, Yung-Chang Huang, Shih-Chieh Chang, Wen-Ben Jone:
Design and design automation of rectification logic for engineering change. ASP-DAC 2005: 1006-1009 - [c31]Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh:
Power minimization for dynamic PLAs. ASP-DAC 2005: 1010-1013 - [c30]Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu, Shih-Chieh Chang:
FPGA technology mapping optimization by rewiring algorithms. ISCAS (6) 2005: 5653-5656 - 2004
- [c29]Swaroop Ghosh, K. W. Lai, Wen-Ben Jone, Shih-Chieh Chang:
Scan Chain Fault Identification Using Weight-Based Codes for SoC Circuits. Asian Test Symposium 2004: 210-215 - [c28]Shih-Chieh Chang, Cheng-Tao Hsieh, Kai-Chiang Wu:
Re-synthesis for delay variation tolerance. DAC 2004: 814-819 - [c27]Cheng-Tao Hsieh, Jian-Cheng Lin, Shih-Chieh Chang:
A vectorless estimation of maximum instantaneous current for sequential circuits. ICCAD 2004: 537-540 - 2003
- [j14]J. H. Jiang, Wen-Ben Jone, Shih-Chieh Chang, Swaroop Ghosh:
Embedded core test generation using broadcast test architecture and netlist scrambling. IEEE Trans. Reliab. 52(4): 435-443 (2003) - 2002
- [j13]Yin-He Su, Ching-Hwa Cheng, Shih-Chieh Chang:
Novel Techniques for Improving Testability Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2901-2912 (2002) - [j12]Tzyy-Kuen Tien, Shih-Chieh Chang, Tong-Kai Tsai:
Crosstalk alleviation for dynamic PLAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(12): 1416-1424 (2002) - [c26]Tzyy-Kuen Tien, Tong-Kai Tsai, Shih-Chieh Chang:
Crosstalk Alleviation for Dynamic PLAs. DATE 2002: 683-687 - [c25]Jiann-Chyi Rau, Yan-Min Chen, Shih-Chieh Chang:
A don't-care based image circuit for function verification. ISCAS (5) 2002: 325-328 - 2001
- [j11]Shih-Chieh Chang, Jiann-Chyi Rau:
A timing-driven pseudoexhaustive testing for VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1): 147-158 (2001) - [j10]Shih-Chieh Chang, Ching-Hwa Cheng, Wen-Ben Jone, Shin-De Lee, Jinn-Shyan Wang:
Charge-sharing alleviation and detection for CMOS domino circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(2): 266-280 (2001) - [j9]Shih-Chieh Chang, Zhong-Zhen Wu:
Theorems and extensions of single wire replacement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(9): 1159-1164 (2001) - [j8]Wen-Ben Jone, Der-Cheng Huang, Shih-Chieh Chang, Sunil R. Das:
Defect Level Estimation for Pseudorandom Testing Using Stochastic Analysis. VLSI Design 12(4): 457-474 (2001) - [j7]Shih-Chieh Chang, Kwen-Yo Chen, Ching-Hsiang Cheng, Wen-Ben Jone, Sunil R. Das:
Random Pattern Testability Enhancement by Circuit Rewiring. VLSI Design 12(4): 537-549 (2001) - [c24]J. H. Jiang, Shih-Chieh Chang, Wen-Ben Jone:
Embedded Core Testing Using Broadcast Test Architecture. DFT 2001: 95-103 - 2000
- [j6]Shih-Chieh Chang, Wen-Ben Jone, Shi-Sen Chang:
TAIR: testability analysis by implication reasoning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(1): 152-160 (2000) - [c23]Yin-He Su, Ching-Hwa Cheng, Shih-Chieh Chang:
Novel techniques for improving testability analysis. Asian Test Symposium 2000: 392-397 - [c22]Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang:
Charge sharing fault analysis and testing for CMOS domino logic circuits. Asian Test Symposium 2000: 435-440 - [c21]Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone:
Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits. DFT 2000: 329-337 - [c20]Ching-Hwa Cheng, Shih-Chieh Chang, Shin-De Li, Wen-Ben Jone, Jinn-Shyan Wang:
Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation. ICCAD 2000: 387-390 - [c19]Shih-Chieh Chang, Zhong-Zhen Wu, He-Zhe Yu:
Wire Reconnections Based on Implication Flow Graph. ICCAD 2000: 533-536 - [c18]Jiann-Chyi Rau, Yan-Min Chen, Shih-Chieh Chang:
A compact factored form for a Boolean function. ISCAS 2000: 317-320 - [c17]Shih-Chieh Chang, Jiann-Chyi Rau:
A timing-driven pseudo-exhaustive testing of VLSI circuits. ISCAS 2000: 665-668 - [c16]Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone:
Charge Sharing Fault Analysis and Testing for CMOS Domino Logic Circuits. LATW 2000: 59-64
1990 – 1999
- 1999
- [j5]Shih-Chieh Chang, Lukas P. P. P. van Ginneken, Malgorzata Marek-Sadowska:
Circuit Optimization by Rewiring. IEEE Trans. Computers 48(9): 962-970 (1999) - [j4]Shih-Chieh Chang, David Ihsin Cheng:
Efficient Boolean division and substitution using redundancy addition and removing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(8): 1096-1106 (1999) - [c15]Ching-Wei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone:
Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications. DAC 1999: 68-71 - [c14]Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone:
Charge Sharing Fault Detection for CMOS Domino Logic Circuits. DFT 1999: 77-85 - [c13]Shih-Chieh Chang, Jung-Cheng Chuang, Zhong-Zhen Wu:
Synthesis for multiple input wires replacement of a gate for wiring consideration. ICCAD 1999: 115-119 - [c12]Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone:
Power reduction through iterative gate sizing and voltage scaling. ISCAS (1) 1999: 246-249 - 1998
- [c11]Shih-Chieh Chang, David Ihsin Cheng:
Efficient Boolean Division and Substitution. DAC 1998: 342-347 - [c10]Wen-Ben Jone, Jiann-Chyi Rau, Shih-Chieh Chang, Yu-Liang Wu:
A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits. ITC 1998: 322-330 - [c9]Shih-Chieh Chang, Shi-Sen Chang, Wen-Ben Jone, Chien-Chung Tsai:
A novel combinational testability analysis by considering signal correlation. ITC 1998: 658-667 - 1997
- [j3]Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska:
Postlayout logic restructuring using alternative wires. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(6): 587-596 (1997) - 1996
- [j2]Shih-Chieh Chang, Malgorzata Marek-Sadowska, TingTing Hwang:
Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(10): 1226-1236 (1996) - [j1]Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng:
Perturb and simplify: multilevel Boolean network optimizer. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12): 1494-1504 (1996) - [c8]Shih-Chieh Chang, Malgorzata Marek-Sadowska:
Perturb and Simplify: Optimizing Combinational Circuits with External Don't Cares. ED&TC 1996: 402-406 - [c7]Shih-Chieh Chang, Lukas P. P. P. van Ginneken, Malgorzata Marek-Sadowska:
Fast Boolean optimization by rewiring. ICCAD 1996: 262-269 - 1995
- [c6]Chih-Chang Lin, Kuang-Chien Chen, Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng:
Logic Synthesis for Engineering Change. DAC 1995: 647-652 - [c5]Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng:
An Efficient Algorithm for Local Don't Care Sets Calculation. DAC 1995: 663-667 - 1994
- [c4]Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska:
Layout Driven Logic Synthesis for FPGAs. DAC 1994: 308-313 - [c3]Shih-Chieh Chang, David Ihsin Cheng, Malgorzata Marek-Sadowska:
Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions. EDAC-ETC-EUROASIC 1994: 620-624 - [c2]Shih-Chieh Chang, Malgorzata Marek-Sadowska:
Perturb and simplify: multi-level boolean network optimizer. ICCAD 1994: 2-5 - 1992
- [c1]Shih-Chieh Chang, Malgorzata Marek-Sadowska:
Technology Mapping via Transformations of Function Graphs. ICCD 1992: 159-162
Coauthor Index
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