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Bodhisatwa Sadhu
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2020 – today
- 2023
- [j17]Chihiro Kamidaki, Yuma Okuyama, Tatsuo Kubo, Wooram Lee, Caglar Ozdag, Bodhisatwa Sadhu, Yo Yamaguchi, Ning Guan:
A 24-30GHz Power Amplifier with >20-dBm Psat and <0.1-dB AM-AM Distortion for 5G Applications in 130-nm SiGe BiCMOS. IEICE Trans. Electron. 106(11): 625-634 (2023) - 2022
- [j16]Bodhisatwa Sadhu
, Arun Paidimarri
, Duixian Liu
, Mark Yeck
, Caglar Ozdag
, Yujiro Tojo, Wooram Lee, Kevin Xiaoxiong Gu
, Jean-Olivier Plouchart, Christian W. Baks, Yusuke Uemichi, Sudipto Chakraborty, Yo Yamaguchi, Ning Guan, Alberto Valdes-Garcia
:
A 24-30-GHz 256-Element Dual-Polarized 5G Phased Array Using Fast On-Chip Beam Calculators and Magnetoelectric Dipole Antennas. IEEE J. Solid State Circuits 57(12): 3599-3616 (2022) - [c16]Bodhisatwa Sadhu, Arun Paidimarri
, Wooram Lee
, Mark Yeck, Caglar Ozdag, Yujiro Tojo, Jean-Olivier Plouchart, Xiaoxiong Gu, Yusuke Uemichi, Sudipto Chakraborty, Yo Yamaguchi, Ning Guan, Alberto Valdes-Garcia:
A 24-to-30GHz 256-Element Dual-Polarized 5G Phased Array with Fast Beam-Switching Support for >30, 000 Beams. ISSCC 2022: 436-438 - 2021
- [c15]Bodhisatwa Sadhu, Matteo Bassi, Vito Giannini:
Session 14 Overview: mm-Wave Transceivers for Communication and Radar Wireless Subcommittee. ISSCC 2021: 216-217 - 2020
- [j15]Bodhisatwa Sadhu
, Alberto Valdes-Garcia
, Jean-Olivier Plouchart, Herschel A. Ainspan, Arpit K. Gupta, Mark A. Ferriss, Mark Yeck
, Mihai Sanduleanu
, Xiaoxiong Gu
, Christian W. Baks, Duixian Liu, Daniel J. Friedman:
A 250-mW 60-GHz CMOS Transceiver SoC Integrated With a Four-Element AiP Providing Broad Angular Link Coverage. IEEE J. Solid State Circuits 55(6): 1516-1529 (2020)
2010 – 2019
- 2018
- [j14]Bodhisatwa Sadhu
, Tejasvi Anand
, Scott K. Reynolds:
A Fully Decoupled LC Tank VCO Topology for Amplitude Boosted Low Phase Noise Operation. IEEE J. Solid State Circuits 53(9): 2488-2499 (2018) - [c14]Alberto Valdes-Garcia, Bodhisatwa Sadhu, Xiaoxiong Gu, Jean-Olivier Plouchart, Mark Yeck, Daniel J. Friedman:
Scaling Millimeter-Wave Phased Arrays: Challenges and Solutions. BCICTS 2018: 80-84 - [c13]Alberto Valdes-Garcia, Bodhisatwa Sadhu, Xiaoxiong Gu, Yahya M. Tousi, Duixian Liu, Scott K. Reynolds, Joakim Hallin, Stefan Sahl, Leonard Rexberg:
Circuit and antenna-in-package innovations for scaled mmWave 5G phased array modules. CICC 2018: 1-8 - [c12]Bodhisatwa Sadhu, Arun Paidimarri
, Mark A. Ferriss, Mark Yeck, Xiaoxiong Gu, Alberto Valdes-Garcia:
A 128-element Dual-Polarized Software-Defined Phased Array Radio for mm-wave 5G Experimentation. mmNets 2018: 21-25 - [c11]Xiaoxiong Gu, Bodhisatwa Sadhu, Duixian Liu, Christian W. Baks, Alberto Valdes-Garcia:
Antenna-in-package design and module integration for millimeter-wave communication and 5G. VLSI-DAT 2018: 1-2 - 2017
- [j13]Bodhisatwa Sadhu, Sorin P. Voinigescu:
Introduction to the Special Section on the 2016 IEEE BCTM and IEEE CSICS. IEEE J. Solid State Circuits 52(9): 2224-2225 (2017) - [j12]Bodhisatwa Sadhu
, Yahya M. Tousi, Joakim Hallin, Stefan Sahl, Scott K. Reynolds, Orjan Renstrom, Kristoffer Sjogren, Olov Haapalahti, Nadav Mazor
, Bo Bokinge, Gustaf Weibull, Håkan Bengtsson, Anders Carlinger, Eric Westesson, Jan-Erik Thillberg
, Leonard Rexberg, Mark Yeck
, Xiaoxiong Gu
, Mark A. Ferriss, Duixian Liu, Daniel J. Friedman, Alberto Valdes-Garcia:
A 28-GHz 32-Element TRX Phased-Array IC With Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications. IEEE J. Solid State Circuits 52(12): 3373-3391 (2017) - [c10]Bodhisatwa Sadhu, Yahya M. Tousi, Joakim Hallin, Stefan Sahl, Scott K. Reynolds, Orjan Renstrom, Kristoffer Sjogren, Olov Haapalahti, Nadav Mazor, Bo Bokinge, Gustaf Weibull, Håkan Bengtsson, Anders Carlinger, Eric Westesson, Jan-Erik Thillberg, Leonard Rexberg, Mark Yeck, Xiaoxiong Gu, Daniel J. Friedman, Alberto Valdes-Garcia:
7.2 A 28GHz 32-element phased-array transceiver IC with concurrent dual polarized beams and 1.4 degree beam-steering resolution for 5G communication. ISSCC 2017: 128-129 - 2016
- [c9]Mark A. Ferriss, Bodhisatwa Sadhu, Alexander V. Rylyakov, Herschel A. Ainspan, Daniel J. Friedman:
10.8 A 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOs. ISSCC 2016: 196-198 - 2015
- [j11]Xiaoxiong Gu
, Alberto Valdes-Garcia, Arun Natarajan, Bodhisatwa Sadhu, Duixian Liu, Scott K. Reynolds:
W-band scalable phased arrays for imaging and communications. IEEE Commun. Mag. 53(4): 196-204 (2015) - [j10]Bodhisatwa Sadhu
, Mark A. Ferriss, Alberto Valdes-Garcia:
A 52 GHz Frequency Synthesizer Featuring a 2nd Harmonic Extraction Technique That Preserves VCO Performance. IEEE J. Solid State Circuits 50(5): 1214-1223 (2015) - [c8]Mark A. Ferriss, Bodhisatwa Sadhu, Alexander V. Rylyakov, Herschel A. Ainspan, Daniel J. Friedman:
10.9 A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme. ISSCC 2015: 1-3 - 2014
- [j9]Bodhisatwa Sadhu, Martin Sturm, Brian M. Sadler
, Ramesh Harjani:
Building an on-chip spectrum sensor for cognitive radios. IEEE Commun. Mag. 52(4): 92-100 (2014) - [j8]Jean-Olivier Plouchart, Fa Wang, Xin Li, Benjamin D. Parker, Mihai A. T. Sanduleanu
, Andreea Balteanu, Bodhisatwa Sadhu, Alberto Valdes-Garcia, Daniel J. Friedman:
Adaptive Circuit Design Methodology and Test Applied to Millimeter-Wave Circuits. IEEE Des. Test 31(6): 8-18 (2014) - [j7]Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu
, Benjamin D. Parker, Alberto Valdes-Garcia, Mihai A. T. Sanduleanu
, José A. Tierno, Daniel J. Friedman:
Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(8): 2243-2252 (2014) - 2013
- [j6]Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, José A. Tierno, Aydin Babakhani, Soner Yaldiz, Alberto Valdes-Garcia, Bodhisatwa Sadhu
, Daniel J. Friedman:
An Integral Path Self-Calibration Scheme for a Dual-Loop PLL. IEEE J. Solid State Circuits 48(4): 996-1008 (2013) - [j5]Bodhisatwa Sadhu
, Mark A. Ferriss, Arun Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott K. Reynolds, Xin Li, Lawrence T. Pileggi, Ramesh Harjani, José A. Tierno, Daniel J. Friedman:
A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing. IEEE J. Solid State Circuits 48(5): 1138-1150 (2013) - [j4]Bodhisatwa Sadhu
, Martin Sturm, Brian M. Sadler
, Ramesh Harjani:
Analysis and Design of a 5 GS/s Analog Charge-Domain FFT for an SDR Front-End in 65 nm CMOS. IEEE J. Solid State Circuits 48(5): 1199-1211 (2013) - [j3]Bodhisatwa Sadhu
, Mark A. Ferriss, Arun S. Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott K. Reynolds, Xin Li, Lawrence T. Pillage, Ramesh Harjani, José A. Tierno, Daniel J. Friedman:
Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing". IEEE J. Solid State Circuits 48(6): 1539 (2013) - [j2]Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu
, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Larry T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman:
A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(8): 2009-2017 (2013) - [j1]Sachin Kalia, Satwik A. Patnaik, Bodhisatwa Sadhu
, Martin Sturm, Mohammad Elbadry, Ramesh Harjani:
Multi-Beam Spatio-Spectral Beamforming Receiver for Wideband Phased Arrays. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(8): 2018-2029 (2013) - [c7]Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu
, Benjamin D. Parker, Alberto Valdes-Garcia, Mihai A. T. Sanduleanu
, José A. Tierno, Daniel J. Friedman:
Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion. CICC 2013: 1-4 - 2012
- [c6]Satwik A. Patnaik, Sachin Kalia, Bodhisatwa Sadhu
, Martin Sturm, Mohammad Elbadry, Ramesh Harjani:
An 8GHz multi-beam spatio-spectral beamforming receiver using an all-passive discrete time analog baseband in 65nm CMOS. CICC 2012: 1-4 - [c5]Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu
, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Lawrence T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman:
A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS. CICC 2012: 1-4 - [c4]Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, Aydin Babakhani, Soner Yaldiz, Bodhisatwa Sadhu
, Alberto Valdes-Garcia, José A. Tierno, Daniel J. Friedman:
An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS. VLSIC 2012: 176-177 - 2010
- [c3]Bodhisatwa Sadhu, Ramesh Harjani:
Capacitor bank design for wide tuning range LC VCOs: 850MHz-7.1GHz (157%). ISCAS 2010: 1975-1978
2000 – 2009
- 2009
- [c2]Bodhisatwa Sadhu
, Jaehyup Kim, Ramesh Harjani:
A CMOS 3.3-8.4 GHz wide tuning range, low phase noise LC VCO. CICC 2009: 559-562 - 2008
- [c1]Bodhisatwa Sadhu
, Umaikhe E. Omole, Ramesh Harjani:
Modeling and synthesis of wide-band switched-resonators for VCOs. CICC 2008: 225-228
Coauthor Index
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