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Kazuhiko Ohno
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2010 – 2019
- 2018
- [c15]Masato Kitou, Takahiro Sasaki, Kazuhiko Ohno:
Performance Evaluation of Dynamic Cell Allocation Cache Using Cycle Accurate Simulator. CANDAR Workshops 2018: 555-557 - 2017
- [c14]Kazuhiko Ohno, Tomoki Nitta, Hiroto Nakai:
SPH-based Fluid Simulation on GPU Using Verlet List and Subdivided Cell-Linked List. CANDAR 2017: 132-138 - 2016
- [j4]Kazuhiko Ohno, Rei Yamamoto, Hiroaki Tanaka:
Dynamic Task Scheduling Scheme for a GPGPU Programming Framework. Int. J. Netw. Comput. 6(2): 290-308 (2016) - 2015
- [j3]Kazuhiko Ohno, Tomoharu Kamiya, Takanori Maruyama, Masaki Matsumoto:
Automatic Optimization of Thread Mapping for a GPGPU Programming Framework. Int. J. Netw. Comput. 5(2): 253-271 (2015) - [c13]Kazuhiko Ohno, Rei Yamamoto:
Dynamic Task Scheduling Scheme for a GPGPU Programming Framework. CANDAR 2015: 181-187 - 2014
- [c12]Kazuhiko Ohno, Tomoharu Kamiya, Takanori Maruyama, Masaki Matsumoto:
Automatic Optimization of Thread Mapping for a GPGPU Programming Framework. CANDAR 2014: 198-204 - 2013
- [j2]Takahiro Sasaki, Tomoyuki Nakabayashi, Kazumasa Nomura, Kazuhiko Ohno, Toshio Kondo:
Design and evaluation of fine-grain-mode transition method based on dynamic memory access analysing for variable stages pipeline processor. IET Comput. Digit. Tech. 7(1): 41-47 (2013) - [j1]Tomoyuki Nakabayashi, Takahiro Sasaki, Hitoshi Nakamura, Kazuhiko Ohno, Toshio Kondo:
Energy Optimization using Fine-Grain Variable Stages Pipeline Processor Chip. Int. J. Netw. Comput. 3(2): 192-204 (2013) - 2012
- [c11]Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo:
Measurement of Low-Energy Processor Chip Using Fine-Grain Variable Stages Pipeline Architecture. ICNC 2012: 293-297 - 2011
- [c10]Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo:
Design and evaluation of variable stages pipeline processor chip. ASP-DAC 2011: 95-96 - [c9]Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo:
Low power semi-static TSPC D-FFs using split-output latch. ISOCC 2011: 167-170 - 2010
- [c8]Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo:
Design and Evaluation of Variable Stages Pipeline Processor Chip. ISIA 2010: 220-226 - [c7]Nobuyuki Matsubara, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo:
Evaluation of Variable Level Cache. ISIA 2010: 227-233
2000 – 2009
- 2002
- [c6]Haruyuki Matsuo, Shigeru Imafuku, Kazuhiko Ohno, Hiroshi Nakashima:
Shaman: A Distributed Simulator for Shared Memory Multiprocessors. MASCOTS 2002: 347-355 - 2001
- [c5]Shigeru Imafuku, Kazuhiko Ohno, Hiroshi Nakashima:
Reference Filtering for Distributed Simulation of Shared Memory Multiprocessors. Annual Simulation Symposium 2001: 219-226 - 2000
- [c4]Takayuki Sato, Kazuhiko Ohno, Hiroshi Nakashima:
A Mechanism for Speculative Memory Accesses Following Synchronizing Operations. IPDPS 2000: 145-154 - [c3]Kazuhiko Ohno, Shigehiro Yamamoto, Takanori Okano, Hiroshi Nakashima:
Orgel: A Parallel Programming Language with Declarative Communication Streams. ISHPC 2000: 344-354
1990 – 1999
- 1997
- [c2]Kazuhiko Ohno, Masahiko Ikawa, Masahiro Goshima, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita:
Efficient Goal Scheduling in Concurrent Logic Language using Type-Based Dependency Analysis. ASIAN 1997: 268-282 - [c1]Kazuhiko Ohno, Masahiko Ikawa, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita, Masahiro Goshima:
Improvement of message communication in concurrent logic language. PASCO 1997: 156-164
Coauthor Index
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