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Junyong Deng
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2020 – today
- 2024
- [j3]Junyong Deng, Shuai Liu, Xiaona Qin:
Watermarking-based remote secure sequential fusion estimation under the event-triggered mechanism. J. Frankl. Inst. 361(12): 106993 (2024) - 2023
- [j2]Kangle Li, Lin Jiang
, Xingjie Huang, Kun Yang, Xiaoyan Xie, Junyong Deng, Rui Shan:
DMPRA: A Dynamic Reconfiguration Mechanism for a Dual-Mode Programmable Reconfigurable Array Architecture. J. Circuits Syst. Comput. 32(9): 2350157:1-2350157:27 (2023) - [c7]Kai Zhou
, Junyong Deng
, Yukai Zeng
:
Design and Memory Access Optimization of Graph processing Processor design Based on RISC-V. AIPR 2023: 576-583 - [c6]Junyong Deng
, Jingwen Deng
, Xiaoyan Xie
, Pan Zhang
, Junjie Wang
, Kai Zhou
:
Design and Implementation of SSSP Accelerator based-on Reconfigurable and Programmable Computing Array. AIPR 2023: 954-962 - 2021
- [c5]Junyong Deng, Qingqing Ma, Zekun Ye:
Performance Characterization of Rasterization Algorithms for Reconfigurable Graphics Processor. APSIPA ASC 2021: 133-140 - 2020
- [j1]Junyong Deng, Qinzhe Wu, Xiaoyan Wu, Shuang Song, Joseph Dean, Lizy Kurian John:
Demystifying graph processing frameworks and benchmarks. Sci. China Inf. Sci. 63(12) (2020)
2010 – 2019
- 2019
- [c4]Junyong Deng, Haoyue Wu, Rui Shan, Yiwen Fu, Xinchuang Liu, Ping Wang:
NPFONoC: A Low-loss, Non-blocking, Scalable Passive Optical Interconnect Network-on-Chip Architecture. APSIPA 2019: 1443-1448 - [d2]Qinzhe Wu
, Steven Flolid, Shuang Song, Junyong Deng, Lizy K. John
:
UT-LCA/Scalability-Phase-Simpoint-of-SPEC-CPU2017: SPEC CPU2017 Integer Speed Suite SimPoint Pinballs. Version v1.3. Zenodo, 2019 [all versions] - [d1]Qinzhe Wu
, Steven Flolid, Shuang Song, Junyong Deng, Lizy K. John
:
UT-LCA/Scalability-Phase-Simpoint-of-SPEC-CPU2017: SPEC CPU2017 Integer Speed Suite SimPoint Pinballs. Version v1.3. Zenodo, 2019 [all versions] - 2018
- [c3]Qinzhe Wu, Steven Flolid, Shuang Song, Junyong Deng, Lizy K. John:
Invited Paper for the Hot Workloads Special Session Hot Regions in SPEC CPU2017. IISWC 2018: 71-77 - 2016
- [c2]Lin Jiang, Qian Yang, Yun Zhu, Junyong Deng:
A parallel implementation of deblocking filter based on video array architecture for HEVC. IGSC 2016: 1-7
2000 – 2009
- 2009
- [c1]Junyong Deng, Lin Jiang, Zecang Zeng:
Design of Multi-phase Clock Generation and Selection Circuit for CDR. CSIE (3) 2009: 387-391
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