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Rolf Sautter
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2010 – 2019
- 2017
- [c6]Philipp Salz, A. Frisch, Wolfgang Penth, J. Noack, T. Kalla, Rolf Sautter, Michael Kugel, Otto A. Torreiter, G. Sapp, Mike Lee, Eric Fluhr, A. Rozenfeld, Jürgen Pille, Dieter F. Wendel:
A system of array families and synthesized soft arrays for the POWER9™ processor in 14nm SOI FinFET technology. ESSCIRC 2017: 303-307 - 2015
- [c5]Alexander Fritsch, Michael Kugel, Rolf Sautter, Dieter F. Wendel, Juergen Pille, Otto A. Torreiter, Shankar Kalyanasundaram, Daniel A. Dobson:
A 4GHz, low latency TCAM in 14nm SOI FinFET technology using a high performance current sense amplifier for AC current surge reduction. ESSCIRC 2015: 343-346 - 2010
- [c4]Jente B. Kuang, Jeremy D. Schaub, Fadi H. Gebara, Dieter F. Wendel, Sudesh Saroop, Tuyet Nguyen, Thomas Fröhnel, Antje Müller, Christopher M. Durham, Rolf Sautter, Bryan Lloyd, Bryan J. Robbins, Juergen Pille, Sani R. Nassif, Kevin J. Nowka:
A 32nm 0.5V-supply dual-read 6T SRAM. CICC 2010: 1-4 - [c3]Jürgen Pille, Dieter F. Wendel, Otto Wagner, Rolf Sautter, Wolfgang Penth, Thomas Fröhnel, Stefan Büttner, Otto A. Torreiter, Martin Eckert, Jose Paredes, David Hrusecky, David Ray, Miles G. Canada:
A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor. ISSCC 2010: 344-345
2000 – 2009
- 2006
- [c2]Nicolas Mäding, Jens Leenstra, Jürgen Pille, Rolf Sautter, Stefan Büttner, Sebastian Ehrenreich, W. Haller:
The vector fixed point unit of the synergistic processor element of the cell architecture processor. DATE Designers' Forum 2006: 244-248 - 2005
- [c1]Nicolas Mäding, Jens Leenstra, Jürgen Pille, Rolf Sautter, Stefan Büttner, Sebastian Ehrenreich, W. Haller:
The vector fixed point unit of the synergistic processor element of the cell architecture processor. ESSCIRC 2005: 203-206 - 2001
- [j1]Jens Leenstra, Jürgen Pille, Antje Müller, Wolfram M. Sauer, Rolf Sautter, Dieter F. Wendel:
A 1.8-GHz instruction window buffer for an out-of-order microprocessor core. IEEE J. Solid State Circuits 36(11): 1628-1635 (2001)
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