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ORCIDShinobu Nagayama
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2020 – today
- 2024
[j22]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Functional Decomposition of Symmetric Multiple-Valued Functions and Their Compact Representation in Decision Diagrams. IEICE Trans. Inf. Syst. 107(8): 922-929 (2024)- [c50]Rie Kometani, Shinobu Nagayama, Martin Lukac, Masato Inagi, Shin'ichi Wakabayashi:
A Proposal of Equivalence Classes in Maximally Asymmetric Functions and Their Application to Benchmark Generation. ISMVL 2024: 59-64 - [c49]Martin Lukac, Krzysztof Podlaski, Shinobu Nagayama, Michitaka Kameyama:
Ternary Function Classification Using Machine Learning. ISMVL 2024: 65-71 - 2023
- [j21]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
On Representation of Maximally Asymmetric Functions Based on Decision Diagrams. FLAP 10(6): 1105-1130 (2023) - [j20]Gaku Kataoka, Masahiro Yamamoto, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi:
Feature Vectors Based on Wire Width and Distance for Lithography Hotspot Detection. IPSJ Trans. Syst. LSI Des. Methodol. 16: 2-11 (2023) - [c48]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Decomposition-Based Representation of Symmetric Multiple-Valued Functions. ISMVL 2023: 76-81 - [i1]Jon T. Butler, Tsutomu Sasao, Shinobu Nagayama:
On the distribution of sensitivities of symmetric Boolean functions. CoRR abs/2306.14401 (2023) - 2022
- [j19]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
A Fast Method for Exactly Optimum Linear Decomposition of Index Generation Functions. J. Multiple Valued Log. Soft Comput. 38(3-4): 387-405 (2022) - [c47]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
On Decision Diagrams for Maximally Asymmetric Functions. ISMVL 2022: 164-169 - 2021
- [c46]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Improvement in the Quality of Solutions of a Heuristic Linear Decomposer for Index Generation Functions. ISMVL 2021: 13-18 - 2020
- [c45]Jon T. Butler, Tsutomu Sasao, Shinobu Nagayama:
Properties of Multiple-Valued Partition Functions. ISMVL 2020: 82-87 - [c44]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
On Optimum Linear Decomposition of Symmetric Index Generation Functions. ISMVL 2020: 130-136
2010 – 2019
- 2019
- [c43]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
A Dynamic Programming Based Method for Optimum Linear Decomposition of Index Generation Functions. ISMVL 2019: 144-149 - 2018
- [j18]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
An Exact Optimization Method using ZDDs for Linear Decomposition of Symmetric Index Generation Functions. FLAP 5(9): 1849-1866 (2018) - [c42]Yuri Itotani, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi:
An Approximate Nearest Neighbor Search Algorithm Using Distance-Based Hashing. DEXA (2) 2018: 203-213 - [c41]Gaku Kataoka, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi:
Novel Feature Vectors Considering Distances between Wires for Lithography Hotspot Detection. DSD 2018: 85-90 - [c40]Toshitaka Ito, Yuri Itotani, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi:
A Nearest Neighbor Search Engine Using Distance-Based Hashing. FPT 2018: 150-157 - [c39]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
An Exact Optimization Method Using ZDDs for Linear Decomposition of Index Generation Functions. ISMVL 2018: 144-149 - 2017
- [j17]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
A Balanced Decision Tree Based Heuristic for Linear Decomposition of Index Generation Functions. IEICE Trans. Inf. Syst. 100-D(8): 1583-1591 (2017) - [c38]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
An Exact Optimization Algorithm for Linear Decomposition of Index Generation Functions. ISMVL 2017: 161-166 - 2016
- [c37]Yuto Arai, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi:
An efficient FPGA implementation of Mahalanobis distance-based outlier detection for streaming data. FPT 2016: 257-260 - [c36]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
An Efficient Heuristic for Linear Decomposition of Index Generation Functions. ISMVL 2016: 96-101 - 2015
- [c35]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Mitchell A. Thornton
, Theodore W. Manikas:
Edge Reduction for EVMDDs to Speed Up Analysis of Multi-state Systems. ISMVL 2015: 170-175 - 2014
- [j16]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Mitchell A. Thornton, Theodore W. Manikas:
On Optimizations of Edge-Valued MDDs for Fast Analysis of Multi-State Systems. IEICE Trans. Inf. Syst. 97-D(9): 2234-2242 (2014) - [j15]Leonid V. Moroz, Shinobu Nagayama, Taras Mykytiv, Ihor O. Kirenko, Taras Boretskyy:
Simple Hybrid Scaling-Free CORDIC Solution for FPGAs. Int. J. Reconfigurable Comput. 2014: 615472:1-615472:4 (2014) - [j14]Yoichi Wakaba, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi:
An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating. Inf. Media Technol. 9(4): 466-474 (2014) - [j13]Yoichi Wakaba, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi:
An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating. IPSJ Trans. Syst. LSI Des. Methodol. 7: 110-118 (2014) - [j12]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
EVMDD-Based Analysis and Diagnosis Methods of Multi-State Systems with Multi-State Components. J. Multiple Valued Log. Soft Comput. 22(1-2): 59-78 (2014) - [j11]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Piecewise Arithmetic Expressions of Numeric Functions and Their Application to Design of Numeric Function Generators. J. Multiple Valued Log. Soft Comput. 23(3-4): 293-313 (2014) - [c34]Hiroki Nishiyama, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama, Keisuke Inoue, Mineo Kaneko:
An ILP-Based Optimal Circuit Mapping Method for PLDs. IPDPS Workshops 2014: 251-256 - [c33]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Mitchell A. Thornton, Theodore W. Manikas:
Analysis Methods of Multi-state Systems Partially Having Dependent Components Using Multiple-Valued Decision Diagrams. ISMVL 2014: 190-195 - [c32]Mitchell A. Thornton, Theodore W. Manikas, Stephen A. Szygenda, Shinobu Nagayama:
System Probability Distribution Modeling Using MDDs. ISMVL 2014: 196-201 - [c31]Ryutaro Kurai, Norihito Yasuda, Hiroki Arimura, Shinobu Nagayama, Shin-ichi Minato:
Fast Regular Expression Matching Based On Dual Glushkov NFA. Stringology 2014: 3-16 - 2013
- [c30]Yoichi Wakaba, Shinobu Nagayama, Shin'ichi Wakabayashi, Masato Inagi:
A Flexible and Compact Regular Expression Matching Engine Using Partial Reconfiguration for FPGA. DSD 2013: 293-296 - [c29]Yasuhiro Shintani, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi:
A Multithreaded Parallel Global Routing Method with Overlapped Routing Regions. DSD 2013: 591-597 - [c28]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Minimization of the Number of Edges in an EVMDD by Variable Grouping for Fast Analysis of Multi-State Systems. ISMVL 2013: 284-289 - 2012
- [c27]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Analysis of Multi-state Systems with Multi-state Components Using EVMDDs. ISMVL 2012: 122-127 - 2011
- [c26]Satoru Nakano, Yoichi Wakaba, Shinobu Nagayama, Shin'ichi Wakabayashi:
A Design Method for Programmable Two-Variable Discrete Function Generators Using Spline and Bilinear Interpolations. DSD 2011: 701-707 - [c25]Yoichi Wakaba, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama:
An Efficient Hardware Matching Engine for Regular Expression with Nested Kleene Operators. FPL 2011: 157-161 - [c24]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Numeric Function Generators Using Piecewise Arithmetic Expressions. ISMVL 2011: 16-21 - 2010
- [j10]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
A Systematic Design Method for Two-Variable Numeric Function Generators Using Multiple-Valued Decision Diagrams. IEICE Trans. Inf. Syst. 93-D(8): 2059-2067 (2010) - [j9]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Programmable Architectures and Design Methods for Two-Variable Numeric Function Generators. Inf. Media Technol. 5(2): 412-423 (2010) - [j8]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Programmable Architectures and Design Methods for Two-Variable Numeric Function Generators. IPSJ Trans. Syst. LSI Des. Methodol. 3: 118-129 (2010) - [c23]Yuichiro Utan, Shin'ichi Wakabayashi, Shinobu Nagayama:
An FPGA-based text search engine for approximate regular expression matching. FPT 2010: 184-191 - [c22]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Floating-Point Numeric Function Generators Based on Piecewise-Split EVMDDs. ISMVL 2010: 223-228
2000 – 2009
- 2009
- [j7]Shinobu Nagayama, Tsutomu Sasao:
Complexities of Graph-Based Representations for Elementary Functions. IEEE Trans. Computers 58(1): 106-119 (2009) - [c21]Yosuke Kawanaka, Shin'ichi Wakabayashi, Shinobu Nagayama:
A Systolic String Matching Algorithm for High-Speed Recognition of a Restricted Regular Set. ERSA 2009: 151-157 - [c20]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Floating-Point Numerical Function Generators Using EVMDDs for Monotone Elementary Functions. ISMVL 2009: 349-355 - 2008
- [c19]Shinobu Nagayama, Jon T. Butler, Tsutomu Sasao:
Programmable Numerical Function Generators for Two-Variable Functions. DSD 2008: 891-898 - [c18]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Numerical function generators using bilinear interpolation. FPL 2008: 463-466 - [c17]Yosuke Kawanaka, Shin'ichi Wakabayashi, Shinobu Nagayama:
A systolic regular expression pattern matching engine and its application to network intrusion detection. FPT 2008: 297-300 - [c16]Shinobu Nagayama, Tsutomu Sasao:
Representations of Two-Variable Elementary Functions Using EVMDDs and their Applications to Function Generators. ISMVL 2008: 50-56 - 2007
- [j6]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2752-2761 (2007) - [j5]Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler:
Numerical Function Generators Using LUT Cascades. IEEE Trans. Computers 56(6): 826-838 (2007) - [c15]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Numerical Function Generators Using Edge-Valued Binary Decision Diagrams. ASP-DAC 2007: 535-540 - [c14]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation. DSD 2007: 280-287 - [c13]Yoshihiro Kimura, Shin'ichi Wakabayashi, Shinobu Nagayama:
A Systolic Algorithm for the Quadratic Assignment Problem and its FPGA Implementation. FPT 2007: 261-264 - [c12]Shinobu Nagayama, Tsutomu Sasao:
Representations of Elementary Functions Using Edge-Valued MDDs. ISMVL 2007: 5 - [c11]Takayoshi Shimazu, Shin'ichi Wakabayashi, Shinobu Nagayama:
A Parallel Multistage Metaheuristic Algorithm for VLSI Floorplanning. PDPTA 2007: 801-807 - [c10]Shinobu Nagayama, Takeshi Hattori:
A Proposal of RM QRM-MLD with Independent Adaptive Control of Surviving Symbol Replica Candidates for MIMO-OFDM System. VTC Fall 2007: 452-456 - 2006
- [j4]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3510-3518 (2006) - [c9]Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Programmable numerical function generators based on quadratic approximation: architecture and synthesis method. ASP-DAC 2006: 378-383 - [c8]Shin'ichi Wakabayashi, Yoshihiro Kimura, Shinobu Nagayama:
FPGA implementation of tabu search for the quadratic assignment problem. FPT 2006: 269-272 - [c7]Tsutomu Sasao, Shinobu Nagayama:
Representations of Elementary Functions Using Binary Moment Diagrams. ISMVL 2006: 28 - [c6]Shinobu Nagayama, Takeshi Hattori:
A Proposal of QRM-MLD for Reduced Complexity of MLD to Detect MIMO Signals in Fading Environment. VTC Fall 2006: 1-5 - 2005
- [j3]Shinobu Nagayama, Alan Mishchenko, Tsutomu Sasao, Jon T. Butler:
Exact and Heuristic Minimization of the Average Path Length in Decision Diagrams. J. Multiple Valued Log. Soft Comput. 11(5-6): 437-465 (2005) - [j2]Shinobu Nagayama, Tsutomu Sasao:
On the optimization of heterogeneous MDDs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(11): 1645-1659 (2005) - [c5]Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler:
Programmable Numerical Function Generators: Architectures and Synthesis Method. FPL 2005: 118-123 - 2004
- [c4]Shinobu Nagayama, Tsutomu Sasao:
Minimization of memory size for heterogeneous MDDs. ASP-DAC 2004: 871-874 - [c3]Shinobu Nagayama, Tsutomu Sasao:
On the Minimization of Average Path Lengths for Heterogeneous MDDs. ISMVL 2004: 216-222 - 2003
- [j1]Shinobu Nagayama, Tsutomu Sasao:
Compact Representations of Logic Functions Using Heterogeneous MDDs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3168-3175 (2003) - [c2]Shinobu Nagayama, Tsutomu Sasao:
Compact Representations of Logic Functions using Heterogeneous MDDs. ISMVL 2003: 247-252 - 2002
- [c1]Shinobu Nagayama, Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura:
Representations of Logic Functions Using QRMDDs. ISMVL 2002: 261-269
Coauthor Index
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