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Chunghee Kim

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2020 – today

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2021
[c8]
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Min-su Kim, Wonhyun Choi, Jong-Woo Kim, Chunghee Kim, Jae-Hyuk Oh, Bai-Sun Kong:
Dynamic Differential Flip-Flop without Explicit Output Latching Stage for High-Speed SoC. ICECS 2021: 1-4

2010 – 2019

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2018
[c7]
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Min-Su Kim, Ah-Reum Kim, Yong-geol Kim, Chunghee Kim, Dong-Yeop Kim, Jong-Woo Kim, Daeseong Lee, Hyun Lee, Jungyul Pyo, Youngmin Shin, Jae Cheol Son:
Contention-Free High-Speed Clock-Gate based on Set/Reset Latch for Wide Voltage Scaling. ISCAS 2018: 1-5
2016
[c6]
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Min-Su Kim, Chunghee Kim, Yong-geol Kim, Ah-Reum Kim, Jikyum Kim, Juhyun Kang, Daeseong Lee, Changjun Choi, Ilsuk Suh, Jungyul Pyo, Youngmin Shin, Jae Cheol Son:
Single-ended D flip-flop with implicit scan mux for high performance mobile AP. SoCC 2016: 91-95
2015
[c5]
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  - conf/isscc/PyoSLBKKSKOLLLH15
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Jungyul Pyo, Youngmin Shin, Hoi-Jin Lee, Sung-il Bae, Min-Su Kim, Kwangil Kim, Ken Shin, Yohan Kwon, Heungchul Oh, Jaeyoung Lim, Dong-Wook Lee, Jongho Lee, Inpyo Hong, Kyungkuk Chae, Heon-Hee Lee, Sung-Wook Lee, Seongho Song, Chunghee Kim, Jin-Soo Park, Heesoo Kim, Sunghee Yun, Ukrae Cho, Jae Cheol Son, Sungho Park:
23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor. ISSCC 2015: 1-3
2013
[c4]
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Min-Su Kim, Hyoungwook Lee, Jin-Soo Park, Chunghee Kim, Juhyun Kang, Ken Shin, Emil Kagramanyan, Gunok Jung, Ukrae Cho, Youngmin Shin, Jae-Cheol Son:
Scan-controlled pulse flip-flops for mobile application processors. ISCAS 2013: 769-772

2000 – 2009

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2008
[j4]
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Gunok Jung, Chunghee Kim, Kyoungkuk Chae, Gi-Ho Park, Sung-Bae Park:
Power and Skew Aware Point Diffusion Clock Network. IEICE Trans. Electron. 91-C(11): 1832-1834 (2008)
2000
[c3]
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Chunghee Kim, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli:
Free MDD-Based Software Optimization Techniques for Embedded Systems. DATE 2000: 14-18

1990 – 1999

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1996
[j3]
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Chunghee Kim, Hyunchul Shin:
A performance-driven logic emulation system: FPGA network design and performance-driven partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(5): 560-568 (1996)
1995
[j2]
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Hyunchul Shin, Chunghee Kim:
Performance-oriented technology mapping for LUT-based FPGA's. IEEE Trans. Very Large Scale Integr. Syst. 3(2): 323-327 (1995)
[c2]
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Chunghee Kim, Hyunchul Shin, Young-Uk Yu:
Performance-driven circuit partitioning for prototyping by using multiple FPGA chips. ASP-DAC 1995
1993
[j1]
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Hyunchul Shin, Chunghee Kim:
A simple yet effective technique for partitioning. IEEE Trans. Very Large Scale Integr. Syst. 1(3): 380-386 (1993)
[c1]
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Hyunchul Shin, Chunghee Kim, Wonjong Kim, Myoungsub Oh, Kwangjoon Rhee, Seogyun Choi, Heasoo Chung:
A combined hierarchical placement algorithm. ICCAD 1993: 164-169

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