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Journal Articles
- 2007
[j4]Robert Ronan, Colin C. Murphy, Tim Kerins, Colm O'hEigeartaigh, Paulo S. L. M. Barreto:
A flexible processor for the characteristic 3 ηT pairing. Int. J. High Perform. Syst. Archit. 1(2): 79-88 (2007)- [j3]Tim Kerins, William P. Marnane
, Emanuel M. Popovici:
Versatile hardware architectures for GF(pm) arithmetic in public key cryptography. Integr. 40(1): 28-35 (2007) - [j2]Robert Ronan, Colm O'hEigeartaigh, Colin C. Murphy, Michael Scott, Tim Kerins:
Hardware acceleration of the Tate pairing on a genus 2 hyperelliptic curve. J. Syst. Archit. 53(2-3): 85-98 (2007) - 2004
- [j1]Alan Daly, William P. Marnane, Tim Kerins, Emanuel M. Popovici:
An FPGA implementation of a GF(p) ALU for encryption processors. Microprocess. Microsystems 28(5-6): 253-260 (2004)
Conference and Workshop Papers
- 2007
- [c12]Robert Ronan, Colm O'hEigeartaigh, Colin C. Murphy, Tim Kerins, Paulo S. L. M. Barreto:
A Reconfigurable Processor for the Cryptographic nT Pairing in Characteristic 3. ITNG 2007: 11-16 - [c11]Lejla Batina, Jorge Guajardo, Tim Kerins, Nele Mentens, Pim Tuyls, Ingrid Verbauwhede:
Public-Key Cryptography for RFID-Tags. PerCom Workshops 2007: 217-222 - 2006
- [c10]Maurice Keller, Tim Kerins, Francis M. Crowe, William P. Marnane:
FPGA Implementation of a GF(2m) Tate Pairing Architecture. ARC 2006: 358-369 - [c9]Robert Ronan, Colm O'hEigeartaigh, Colin C. Murphy, Michael Scott, Tim Kerins:
FPGA acceleration of the tate pairing in characteristic 2. FPT 2006: 213-220 - [c8]Tom Kan, Tim Kerins, Klaus Kursawe:
Security in Next Generation Consumer Electronic Devices. ISSE 2006: 45-53 - [c7]Robert Ronan, Colm O'hEigeartaigh, Colin C. Murphy, Michael Scott, Tim Kerins, William P. Marnane:
An Embedded Processor for a Pairing-Based Cryptosystem. ITNG 2006: 192-197 - 2005
- [c6]Tim Kerins, William P. Marnane, Emanuel M. Popovici, Paulo S. L. M. Barreto:
Efficient Hardware for the Tate Pairing Calculation in Characteristic Three. CHES 2005: 412-426 - [c5]Maurice Keller, Tim Kerins, William P. Marnane:
FPGA Implementation of a GF(24M) Multiplier for use in Pairing Based Cryptosystems. FPL 2005: 594-597 - 2004
- [c4]Tim Kerins, Emanuel M. Popovici, William P. Marnane:
Algorithms and Architectures for Use in FPGA Implementations of Identity Based Encryption Schemes. FPL 2004: 74-83 - [c3]Francis M. Crowe, Alan Daly, Tim Kerins, William P. Marnane:
Single-chip FPGA implementation of a cryptographic co-processor. FPT 2004: 279-285 - 2003
- [c2]Alan Daly, William P. Marnane, Tim Kerins, Emanuel M. Popovici:
Fast Modular Division for Application in ECC on Reconfigurable Logic. FPL 2003: 786-795 - 2002
- [c1]Tim Kerins, Emanuel M. Popovici, William P. Marnane, Patrick Fitzpatrick:
Fully Parameterizable Elliptic Curve Cryptography Processor over GF(2). FPL 2002: 750-759
Informal and Other Publications
- 2006
- [i4]Lejla Batina, Jorge Guajardo, Tim Kerins, Nele Mentens, Pim Tuyls, Ingrid Verbauwhede:
An Elliptic Curve Processor Suitable For RFID-Tags. IACR Cryptol. ePrint Arch. 2006: 227 (2006) - [i3]Robert Ronan, Colm O'hEigeartaigh, Colin C. Murphy, Tim Kerins, Paulo S. L. M. Barreto:
Hardware Implementation of the ηT Pairing in Characteristic 3. IACR Cryptol. ePrint Arch. 2006: 371 (2006) - 2005
- [i2]Tim Kerins, William P. Marnane, Emanuel M. Popovici, Paulo S. L. M. Barreto:
Efficient hardware for the Tate pairing calculation in characteristic three. IACR Cryptol. ePrint Arch. 2005: 65 (2005) - [i1]Robert Ronan, Colm O'hEigeartaigh, Colin C. Murphy, Michael Scott, Tim Kerins, William P. Marnane:
A Dedicated Processor for the eta Pairing. IACR Cryptol. ePrint Arch. 2005: 330 (2005)
Coauthor Index
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