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2010 – 2019
- 2016
[c43]Chi-Ming Lee, Yong-Jyun Huang, Chih-Wei Liu, Yarsun Hsu:
DeAr: A framework for power-efficient and flexible embedded digital signal processor design. APCCAS 2016: 658-661- [c42]Che-Yu Wu, Ching-Te Chiu, Yarsun Hsu:
Binary descriptor based SIFT and hardware implementation. ISCAS 2016: 610-613 - 2015
- [c41]Zhan-Yao Gu, Yarsun Hsu, Chi-Ming Lee:
Message scheduling and timing analysis for flexray dynamic segment by considering slot-multiplexing. ICVES 2015: 56-61 - [c40]Pin Yi Tsai, Yarsun Hsu, Ching-Te Chiu, Tsai-Te Chu:
Accelerating AdaBoost algorithm using GPU for multi-object recognition. ISCAS 2015: 738-741 - 2014
- [c39]Shang-Chieh Lin, Yu-Cheng Liao, Yarsun Hsu:
A Reliable and Secure GPU-Assisted File System. ICA3PP (1) 2014: 71-84 - [c38]Che-Yu Wu, Ching-Te Chiu, Yarsun Hsu:
Object recognition using bag of words with kernels for big data. ICCE-TW 2014: 89-90 - [c37]Jen-Yu Wang, Yarsun Hsu:
A hybrid on-chip network with a low buffer requirement. ICPADS 2014: 273-280 - [c36]Yung-Chou Tsai, Yarsun Hsu:
Design and Evaluation of Dynamically-Allocated Multi-queue Buffers with Multiple Packets for NoC Routers. PAAP 2014: 1-6 - [c35]Shang-Chieh Lin, Yarsun Hsu:
A Runtime Framework for GPGPU. PAAP 2014: 19-22 - 2013
- [j9]Ching-Te Chiu, Yu-Hao Hsu, Wei-Chih Lai, Jen-Ming Wu, Shawn S. H. Hsu, Yang-Syu Lin, Fanta Chen, Min-Sheng Kao, Yarsun Hsu:
Low Propagation Delay Load-Balanced 4 × 4 Switch Fabric IC in 0.13-µm CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. 21(8): 1481-1495 (2013) - 2012
- [j8]Wei-Yu Tsai, Ching-Te Chiu, Jen-Ming Wu, Shawn S. H. Hsu, Yarsun Hsu:
A Novel Low Gate-Count Pipeline Topology With Multiplexer-Flip-Flops for Serial Link. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(11): 2600-2610 (2012) - [j7]Ching-Te Chiu, Yu-Hao Hsu, Jen-Ming Wu, Shuo-Hung Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ming-Chang Du, Ping-Ling Yang, Ming-Hao Lu, Fanta Chen, Hung-Yu Lin, Yarsun Hsu:
An 8 × 8 20 Gbps Reconfigurable Load Balanced TDM Switch IC for High-Speed Networking. J. Signal Process. Syst. 66(1): 57-73 (2012) - [c34]Wei-Chiu Liu, Zhan-Yao Gu, Yarsun Hsu, Ching-Te Chiu:
Cluster-Based CAN with Enhanced Transmission Capability for Vehicle Networks. ICCVE 2012: 43-48 - [c33]Shan-Jung Miao, Yin Men, Yarsun Hsu:
Achieving Global Fairness for On-Chip Network Using Group Allocation. IPDPS Workshops 2012: 930-937 - [c32]Wei-Yu Tsai, Ching-Te Chiu, Jen-Ming Wu, Shawn S. H. Hsu, Yarsun Hsu, Ying-Fang Tsao:
A novel low gate-count serializer topology with Multiplexer-Flip-Flops. ISCAS 2012: 245-248 - 2011
- [c31]Yu-Hao Hsu, Yang-Syu Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Fanta Chen, Min-Sheng Kao, Wei-Chih Lai, Yarsun Hsu:
A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology. ASP-DAC 2011: 105-106 - [c30]Li-Wei Wu, Wei-Xiang Tang, Yarsun Hsu:
A Novel Architecture and Routing Algorithm for Dynamic Reconfigurable Network-on-Chip. ISPA 2011: 177-182 - [c29]Shan-Jung Miao, Yarsun Hsu:
Group allocation: A novel fairness mechanism for on-chip network. NESEA 2011: 1-7 - [c28]Hung-Jen Sun, Yarsun Hsu:
Implementation and analysis of speculative flow control for on-chip interconnection network. NESEA 2011: 1-6 - 2010
- [c27]Tzer-Ta Tseng, Yarsun Hsu:
A Flexible and Cost-Effective File-Wise Reliability Scheme for Storage Systems. HPCC 2010: 427-433 - [c26]Yi-Chiun Fang, Chien-Kai Tseng, Yarsun Hsu:
Emulation of Object-Based Storage Devices by a Virtual Machine. ICA3PP (2) 2010: 166-177 - [c25]Yu-Hao Hsu, Yang-Syu Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Fanta Chen, Min-Sheng Kao, Yarsun Hsu:
A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology. ISCAS 2010: 581-584 - [c24]Wei-Yu Tsai, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu:
A novel MUX-FF circuit for low power and high speed serial link interfaces. ISCAS 2010: 4305-4308 - [c23]Chi-Fu Chang, Yarsun Hsu:
A System Exploration Platform for Network-on-Chip. ISPA 2010: 359-366
2000 – 2009
- 2009
- [c22]Chung-Wen Huang, Wei-Kuan Shih, Yarsun Hsu, Jenq Kuen Lee:
Configurable SID-based multi-core simulators for embedded system education. WESE@ESWEEK 2009: 64-70 - 2008
- [c21]Jwo-An Lin, Yung-Chou Tsai, Tay-Jyi Lin, Yarsun Hsu:
Cycle Stealing and Channel Management for On-Chip Networks. HPCC 2008: 53-60 - [c20]Yu-Hao Hsu, Ming-Hao Lu, Ping-Ling Yang, Fanta Chen, You-Hung Li, Min-Sheng Kao, Chih-Hsing Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu:
A 28Gbps 4×4 switch with low jitter SerDes using area-saving RF model in 0.13µm CMOS technology. ISCAS 2008: 3086-3089 - 2007
- [j6]Sheng-Kai Hung, Yarsun Hsu:
Reliable Parallel File System with Parity Cache Table Support. IEICE Trans. Inf. Syst. 90-D(1): 22-29 (2007) - [c19]Lungpin Yeh, Juei-Ting Sun, Sheng-Kai Hung, Yarsun Hsu:
A Windows-Based Parallel File System. HPCC 2007: 7-18 - [c18]Po-Chun Liu, Sheng-Kai Hung, Yarsun Hsu:
Security Enhancement and Performance Evaluation of an Object-Based Storage System. HPCC 2007: 408-419 - [c17]Ching-Te Chiu, Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ming-Chang Du, Ping-Ling Yang, Ming-Hao Lu, Fanta Chen, Hung-Yu Lin, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu:
A Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC for High-Speed Networking Applications. ISCAS 2007: 2754-2757 - [c16]Hsiang-Ju Hsu, Ching-Te Chiu, Yarsun Hsu:
Design of ultra low power CML MUXs and latches with forward body bias. SoCC 2007: 141-144 - 2006
- [c15]Sheng-Kai Hung, Yarsun Hsu:
Striping Cache: A Global Cache for Striped Network File System. Asia-Pacific Computer Systems Architecture Conference 2006: 387-393 - [c14]Sheng-Kai Hung, Yarsun Hsu:
DPCT: Distributed Parity Cache Table for Redundant Parallel File System. HPCC 2006: 320-329 - 2005
- [c13]Sheng-Kai Hung, Yarsun Hsu:
Modularized Redundant Parallel Virtual File System. Asia-Pacific Computer Systems Architecture Conference 2005: 186-199 - [c12]Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Min-Sheng Kao, Chih-Hsien Jen, Yarsun Hsu:
A 10 Gb/s Wide-Band Current-Mode Logic I/O Interface for High-Speed Interconnect in 0.18μm CMOS Technology. SoCC 2005: 257-260 - 2000
- [c11]Jin-Soo Kim, Yarsun Hsu:
Memory system behavior of Java programs: methodology and analysis. SIGMETRICS 2000: 264-274
1990 – 1999
- 1997
- [c10]Yarsun Hsu:
Parallel Systems and Parallel I/O Technology. ICPADS 1997: 4 - 1996
- [p3]Peter F. Corbett, Dror G. Feitelson
, Sam Fineberg, Yarsun Hsu, Bill Nitzberg, Jean-Pierre Prost, Marc Snir, Bernard Traversat, Parkson Wong:
Overview of the MPI-IO Parallel I/O Interface. Input/Output in Parallel and Distributed Computer Systems 1996: 127-146 - [p2]Edgar T. Kalns, Yarsun Hsu:
Video on Demand Using the Vesta Parallel File System. Input/Output in Parallel and Distributed Computer Systems 1996: 187-204 - [p1]Sandra Johnson Baylor, Caroline Benveniste, Yarsun Hsu:
Performance Evaluation of a Massively Parallel I/O Subsystem. Input/Output in Parallel and Distributed Computer Systems 1996: 293-311 - 1995
- [j5]Peter F. Corbett, Dror G. Feitelson, Jean-Pierre Prost, George S. Almási, Sandra Johnson Baylor, Anthony Bolmarcich, Yarsun Hsu, Julian Satran, Marc Snir, Robert Colao, Brian D. Herr, Joe Kavaky, Thomas R. Morgan, Anthony Zlotek:
Parallel File Systems for the IBM SP Computers. IBM Syst. J. 34(2): 222-248 (1995) - [j4]Dror G. Feitelson, Peter F. Corbett, Sandra Johnson Baylor, Yarsun Hsu:
Parallel I/O subsystems in massively parallel supercomputers. IEEE Parallel Distributed Technol. Syst. Appl. 3(3): 33-47 (1995) - [j3]Ching-Farn Eric Wu, Yarsun Hsu, Yew-Huey Liu:
Efficient Stack Simulation for Set-Associative Virtual Address Cache with Real Tags. IEEE Trans. Computers 44(5): 719-723 (1995) - [c9]Sandra Johnson Baylor, Caroline Benveniste, Yarsun Hsu:
Performance Evaluation of a Parallel I/O Architecture. International Conference on Supercomputing 1995: 404-413 - [c8]Ching-Farn Eric Wu, Yew-Huey Liu, Yarsun Hsu:
Timestamp consistency and trace-driven analysis for distributed parallel systems. IPPS 1995: 680-686 - 1994
- [j2]Sandra Johnson Baylor, Caroline Benveniste, Yarsun Hsu:
Performance evaluation of a massively parallel I/O subsystem. SIGARCH Comput. Archit. News 22(4): 5-10 (1994) - [c7]Jesse Fang, Yarsun Hsu, Shing-Tsaan Huang, Jie-Yong Juang, W. H. Tsai, Horst F. Wedde:
Are We Providing the Right Education for Computer Science/Engineering Students? ICPADS 1994: 14-15 - 1993
- [j1]Ching-Farn Eric Wu, Yarsun Hsu, Yew-Huey Liu:
A Quantitative Evaluation of Cache Types for High-Performance Computer Systems. IEEE Trans. Computers 42(10): 1154-1162 (1993) - [c6]Ching-Farn Eric Wu, Yarsun Hsu, Yew-Huey Liu:
Efficient Stack Simulation for Shared Memory Set-Associative Multiprocessor Caches. ICPP (1) 1993: 163-170 - 1992
- [c5]C. Eric Wu, Yarsun Hsu, Yew-Huey Liu:
Stack simulation for set-associative V/R-type caches. COMPSAC 1992: 332-339 - 1991
- [c4]Sandra Johnson Baylor, Yarsun Hsu:
The Effects of Network Delays on the Performance of MIN-Based Cache Coherence Protocols. ICPP (1) 1991: 292-295 - 1990
- [c3]Sang Lyul Min, Yarsun Hsu, Hyoung-Joo Kim:
A Design of Performance-optimized Control-based Synchronization. CONPAR 1990: 312-323 - [c2]Caroline Benveniste, Yarsun Hsu:
A trace-driven analysis of the 'wrap-around' network. ICCD 1990: 82-85
1980 – 1989
- 1989
- [c1]Shiwei Wang, Yarsun Hsu, C. J. Tan:
A novel message switch for highly parallel systems. ICCD 1989: 150-155
Coauthor Index
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