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ORCIDAntonio Liscidini
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2020 – today
- 2024
[j33]Edoardo Bonizzoni
, Sebastian Hoyos, Antonio Liscidini:
Guest Editorial Special Issue on the 2024 IEEE International Symposium on Circuits and Systems. IEEE Trans. Circuits Syst. II Express Briefs 71(5): 2503 (2024)- [j32]Armin Choopani, Antonio Liscidini:
DC-Coupled Biasing Technique for Quantized-Analog Amplifiers. IEEE Trans. Circuits Syst. II Express Briefs 71(9): 4146-4150 (2024) - [j31]Antonio Liscidini:
Guest Editorial Special Issue on the 2024 ISICAS: A CAS Journal Track Symposium. IEEE Trans. Circuits Syst. II Express Briefs 71(11): 4607 (2024) - [c32]John Zhong, Konstantinos Vasilakopoulos, Antonio Liscidini:
4.5 A Reconfigurable, Multi-Channel Quantized-Analog Transmitter with <-35dB EVM and <-51dBc ACLR in 22nm FDSOI. ISSCC 2024: 84-86 - 2023
- [c31]Tianwen Tang, Antonio Liscidini:
A 22nm 56TOPS/W 6/8-bit Linearly-scalable R-2R Multiply-and-Accumulate Architecture with 2.2ns Latency. ESSCIRC 2023: 473-476 - [c30]Xhulio Selmani, Gurjeet Singh, Rinaldo Castello, Antonio Liscidini:
A 36 GHz Bandwidth, High Linear, Low Power, Driver Modulator, in 28 nm CMOS Technology Based on Quantized-Analog Signal Processing. ISCAS 2023: 1-5 - [c29]Gurjeet Singh, Xhulio Selmani, Rinaldo Castello, Antonio Liscidini:
A Wide Bandwidth, Low Power, Linear Quantized-Analog VGA in 28 nm CMOS Technology and 1.2V Supply. PRIME 2023: 137-140 - 2022
- [j30]Qingnan Yu, Tony Chan Carusone, Antonio Liscidini:
Optimization of Quantized Analog Signal Processing Using Genetic Algorithms and μ-Law. IEEE Open J. Circuits Syst. 3: 38-49 (2022) - [c28]Justin Yonghui Kim, Antonio Liscidini:
A 2GHz voltage mode power scalable RF-Front-End with 2.5dB-NF and 0.5dBm-1dBCP. CICC 2022: 1-2 - 2021
- [j29]Saba Zargham, Zexi Ji, Antonio Liscidini:
A 2.4-GHz 1.3-mW OQPSK RF Front-End TX Based on an Injection-Locked Power Amplifier. IEEE J. Solid State Circuits 56(5): 1541-1552 (2021) - 2020
- [j28]Tuomas Haapala, Antonio Liscidini, Kari A. I. Halonen:
Temperature Compensation of Crystal References in NB-IoT Modems. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(7): 2467-2480 (2020)
2010 – 2019
- 2019
- [j27]Javid Musayev, Antonio Liscidini:
A Quantized Analog RF Front End. IEEE J. Solid State Circuits 54(7): 1929-1940 (2019) - [j26]Sevil Zeynep Lulec, David A. Johns, Antonio Liscidini:
A Third-Order Integrated Passive Switched-Capacitor Filter Obtained With a Continuous-Time Design Approach. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(10): 3643-3652 (2019) - 2018
- [j25]Qiwei Wang, Hajime Shibata, Antonio Liscidini, Anthony Chan Carusone:
A Digital Filtering ADC With Programmable Blocker Cancellation for Wireless Receivers. IEEE J. Solid State Circuits 53(3): 681-691 (2018) - [c27]Zhonghong Jiang, David A. Johns, Antonio Liscidini:
A low-power sub-GHz RF receiver front-end with enhanced blocker tolerance. CICC 2018: 1-4 - [c26]Zexi Ji, Saba Zargham, Antonio Liscidini:
Low-Power QPSK Transmitter Based on an Injection-Locked Power Amplifier. ESSCIRC 2018: 134-137 - [c25]Javid Musayev, Antonio Liscidini:
Quantized Analog RX Front-End for SAW-Less Applications. ESSCIRC 2018: 306-309 - 2017
- [c24]Qiwei Wang, Hajime Shibata, Anthony Chan Carusone, Antonio Liscidini:
A LTE RX front-end with digitally programmable multi-band blocker cancellation in 28nm CMOS. CICC 2017: 1-4 - [c23]Jan van Sinderen, Danielle Griffith, Ken Yamamoto, Antonio Liscidini, Young-sub Yuk:
F4: Wireless low-power transceivers for local and wide-area networks. ISSCC 2017: 509-511 - [c22]Qiwei Wang, Antonio Liscidini, Anthony Chan Carusone:
Filtering ADCs for wireless receivers: A survey. MWSCAS 2017: 997-1000 - 2016
- [j24]Chuanwei Li, Antonio Liscidini:
Class-C PA-VCO Cell for FSK and GFSK Transmitters. IEEE J. Solid State Circuits 51(7): 1537-1546 (2016) - [j23]Edgar Sánchez-Sinencio, Jan Mulder, Antonio Liscidini, Eric A. M. Klumperink, Elad Alon:
Introduction to the December Special Issue on the 2016 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 51(12): 2803-2807 (2016) - [j22]Sevil Zeynep Lulec, David A. Johns, Antonio Liscidini:
A Simplified Model for Passive-Switched-Capacitor Filters With Complex Poles. IEEE Trans. Circuits Syst. II Express Briefs 63-II(6): 513-517 (2016) - [c21]Tian Ya Liu, Antonio Liscidini:
20.9 A 1.92mW filtering transimpedance amplifier for RF current passive mixers. ISSCC 2016: 358-359 - 2015
- [j21]Anith Selvakumar, Meysam Zargham, Antonio Liscidini:
Sub-mW Current Re-Use Receiver Front-End for Wireless Sensor Network Applications. IEEE J. Solid State Circuits 50(12): 2965-2974 (2015) - [j20]Anith Selvakumar, Antonio Liscidini:
Current-Recycling Complex Filter for Bluetooth-Low-Energy Applications. IEEE Trans. Circuits Syst. II Express Briefs 62-II(4): 332-336 (2015) - [c20]Chuanwei Li, Antonio Liscidini:
A current re-use PA-VCO cell for low-power BLE transmitters. ESSCIRC 2015: 172-175 - [c19]Alessandra Pipino, Antonio Liscidini, Karen Wan, Andrea Baschirotto:
Bluetooth low energy receiver system design. ISCAS 2015: 465-468 - [c18]Anith Selvakumar, Meysam Zargham, Antonio Liscidini:
13.6 A 600μW Bluetooth low-energy front-end receiver in 0.13μm CMOS technology. ISSCC 2015: 1-3 - 2014
- [j19]Marco Garampazzi, Stefano Dal Toso, Antonio Liscidini, Danilo Manstretta, P. Mendez, Luca Romanò, Rinaldo Castello:
An Intuitive Analysis of Phase Noise Fundamental Limits Suitable for Benchmarking LC Oscillators. IEEE J. Solid State Circuits 49(3): 635-645 (2014) - [j18]Antonio Liscidini, Luca Fanori, Pietro Andreani, Rinaldo Castello:
A Power-Scalable DCO for Multi-Standard GSM/WCDMA Frequency Synthesizers. IEEE J. Solid State Circuits 49(3): 646-656 (2014) - [j17]Nicola Codega, Paolo Rossi, Alberto Pirola, Antonio Liscidini, Rinaldo Castello:
A Current-Mode, Low Out-of-Band Noise LTE Transmitter With a Class-A/B Power Mixer. IEEE J. Solid State Circuits 49(7): 1627-1638 (2014) - 2013
- [j16]Antonio Liscidini, Douglas Smith:
Introduction to the Special Issue on the 38th European Solid-State Circuits Conference (ESSCIRC). IEEE J. Solid State Circuits 48(7): 1555-1557 (2013) - [j15]Ivan Fabiano, Marco Sosio, Antonio Liscidini, Rinaldo Castello:
SAW-Less Analog Front-End Receivers for TDD and FDD. IEEE J. Solid State Circuits 48(12): 3067-3079 (2013) - [j14]Marco Sosio, Antonio Liscidini, Rinaldo Castello:
An Intuitive Current-Driven Passive Mixer Model Based on Switched-Capacitor Theory. IEEE Trans. Circuits Syst. II Express Briefs 60-II(2): 66-70 (2013) - [c17]Nicola Codega, Antonio Liscidini, Rinaldo Castello:
A low out-of-band noise LTE transmitter with current-mode approach. ESSCIRC 2013: 283-286 - [c16]Ivan Fabiano, Marco Sosio, Antonio Liscidini, Rinaldo Castello:
SAW-less analog front-end receivers for TDD and FDD. ISSCC 2013: 82-83 - [c15]Paolo Rossi, Nicola Codega, Danilo Gerna, Antonio Liscidini, Daniele Ottini, Yong He, Alberto Pirola, Enrico Sacchi, Gregory Uehara, Chao Yang, Rinaldo Castello:
An LTE transmitter using a class-A/B power mixer. ISSCC 2013: 340-341 - [c14]Antonio Liscidini, SeongHwan Cho, Tony Chan Carusone, Tanay Karnik, Mike Keaveney, Brian Otis, Aaron Partridge, Christoph Sandner:
F5: Frequency generation and clock distribution. ISSCC 2013: 508-509 - 2012
- [j13]Woogeun Rhee, Antonio Liscidini, Jae-Yoon Sim, Kenichi Okada, Sudhakar Pamarti:
Clock/Frequency Generation Circuits and Systems. J. Electr. Comput. Eng. 2012: 941653:1-941653:2 (2012) - [j12]Ping Lu, Antonio Liscidini, Pietro Andreani:
A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an Equivalent Resolution of 3.2 ps. IEEE J. Solid State Circuits 47(7): 1626-1635 (2012) - [j11]Luca Vercesi, Luca Fanori, Fernando De Bernardinis, Antonio Liscidini, Rinaldo Castello:
A Dither-Less All Digital PLL for Cellular Transmitters. IEEE J. Solid State Circuits 47(8): 1908-1920 (2012) - [j10]Marco Sosio, Antonio Liscidini, Rinaldo Castello:
A 2G/3G Cellular Analog Baseband Based on a Filtering ADC. IEEE Trans. Circuits Syst. II Express Briefs 59-II(4): 214-218 (2012) - [c13]Antonio Liscidini, Luca Fanori, Pietro Andreani, Rinaldo Castello:
A 36mW/9mW power-scalable DCO in 55nm CMOS for GSM/WCDMA frequency synthesizers. ISSCC 2012: 348-350 - [c12]Luca Fanori, Antonio Liscidini, Pietro Andreani:
A 6.7-to-9.2GHz 55nm CMOS hybrid Class-B/Class-C cellular TX VCO. ISSCC 2012: 354-356 - [c11]Ping Lu, Pietro Andreani, Antonio Liscidini:
A 90nm CMOS gated-ring-oscillator-based 2-dimension Vernier time-to-digital converter. NORCHIP 2012: 1-4 - 2011
- [j9]Alberto Pirola, Antonio Liscidini, Rinaldo Castello:
Corrections to "Current-Mode, WCDMA Channel Filter With In-Band Noise Shaping" [Sep 10 1770-1780]. IEEE J. Solid State Circuits 46(2): 546 (2011) - [c10]Luca Vercesi, Luca Fanori, Fernando De Bernardinis, Antonio Liscidini, Rinaldo Castello:
A dither-less all digital PLL for cellular transmitters. CICC 2011: 1-8 - [c9]Marco Sosio, Antonio Liscidini, Rinaldo Castello, Fernando De Bernardinis:
A complete DVB-T/ATSC tuner analog base-band implemented with a single filtering ADC. ESSCIRC 2011: 391-394 - [c8]Ping Lu, Pietro Andreani, Antonio Liscidini:
A 90nm CMOS gated-ring-oscillator-based Vernier time-to-digital converter for DPLLs. ESSCIRC 2011: 459-462 - 2010
- [j8]Luca Vercesi, Antonio Liscidini, Rinaldo Castello:
Two-Dimensions Vernier Time-to-Digital Converter. IEEE J. Solid State Circuits 45(8): 1504-1512 (2010) - [j7]Marika Tedeschi, Antonio Liscidini, Rinaldo Castello:
Low-Power Quadrature Receivers for ZigBee (IEEE 802.15.4) Applications. IEEE J. Solid State Circuits 45(9): 1710-1719 (2010) - [j6]Alberto Pirola, Antonio Liscidini, Rinaldo Castello:
Current-Mode, WCDMA Channel Filter With In-Band Noise Shaping. IEEE J. Solid State Circuits 45(9): 1770-1780 (2010) - [j5]Luca Fanori, Antonio Liscidini, Rinaldo Castello:
Capacitive Degeneration in LC-Tank Oscillator for DCO Fine-Frequency Tuning. IEEE J. Solid State Circuits 45(12): 2737-2745 (2010) - [c7]Luca Fanori, Antonio Liscidini, Rinaldo Castello:
3.3GHz DCO with a frequency resolution of 150Hz for All-digital PLL. ISSCC 2010: 48-49
2000 – 2009
- 2009
- [c6]Antonio Liscidini, Luca Vercesi, Rinaldo Castello:
Time to digital converter based on a 2-dimensions Vernier architecture. CICC 2009: 45-48 - [c5]Antonio Liscidini, Alberto Pirola, Rinaldo Castello:
A 1.25mW 75dB-SFDR CT filter with in-band noise reduction. ISSCC 2009: 336-337 - 2008
- [j4]Antonio Liscidini, Giuseppe Martini, Daniele Mastantuono, Rinaldo Castello:
Analysis and Design of Configurable LNAs in Feedback Common-Gate Topologies. IEEE Trans. Circuits Syst. II Express Briefs 55-II(8): 733-737 (2008) - [c4]Marika Tedeschi, Antonio Liscidini, Rinaldo Castello:
A 0.23mm2 free coil ZigBee receiver based on a bond-wire self-oscillating mixer. ESSCIRC 2008: 430-433 - [c3]Antonio Liscidini, Marika Tedeschi, Rinaldo Castello:
A 2.4 GHz 3.6mW 0.35mm2 Quadrature Front-End RX for ZigBee and WPAN Applications. ISSCC 2008: 370-371 - 2006
- [j3]Antonio Liscidini, Massimo Brandolini, Davide Sanzogni, Rinaldo Castello:
A 0.13 μm CMOS front-end, for DCS1800/UMTS/802.11b-g with multiband positive feedback low-noise amplifier. IEEE J. Solid State Circuits 41(4): 981-989 (2006) - [j2]Antonio Liscidini, Andrea Mazzanti, Riccardo Tonietto, Luca Vandi, Pietro Andreani, Rinaldo Castello:
Single-Stage Low-Power Quadrature RF Receiver Front-End: The LMV Cell. IEEE J. Solid State Circuits 41(12): 2832-2841 (2006) - [c2]Antonio Liscidini, Cesare Ghezzi, Emanuele Depaoli, Guido Albasini, Ivan Bietti, Rinaldo Castello:
Common Gate Transformer Feedback LNA in a High IIP3 Current Mode RF CMOS Front-End. CICC 2006: 25-28 - [c1]Antonio Liscidini, Andrea Mazzanti, Riccardo Tonietto, Luca Vandi, Pietro Andreani, Rinaldo Castello:
A 5.4mW GPS CMOS Quadrature Front-End Based on a Single-Stage LNA-Mixer-VCO. ISSCC 2006: 1892-1901 - 2005
- [j1]Paolo Rossi, Antonio Liscidini, Massimo Brandolini, Francesco Svelto:
A variable gain RF front-end, based on a Voltage-Voltage feedback LNA, for multistandard applications. IEEE J. Solid State Circuits 40(3): 690-697 (2005)
Coauthor Index
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