0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability.

Tue, 01 Jan 2002 00:00:00 +0100

Hirohito Kikukawa, Shigeki Tomishima , Takaharu Tsuji, Toshiaki Kawasaki, Shouji Sakamoto, Masatoshi Ishikawa, Wataru Abe, Hiroaki Tanizaki, Hiroshi Kato, Toshitaka Uchikoba, Toshihiro Inokuchi, Manabu Senoh, Yoshifumi Fukushima, Mitsutaka Niiro, Masanao Maruta, Akinori Shibayama, Tsukasa Ooishi, Kazunari Takahashi, Hideto Hidaka:
0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability. IEEE J. Solid State Circuits 37(7): 932-940 (2002)