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Byung-Hun Min

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2010 – 2019

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2013
[j2]
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  dblp key:
  - journals/iet-cds/ByunSHMPY13
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  - https://dblp.org/rec/journals/iet-cds/ByunSHMPY13
Sangjin Byun, Chung Hwan Son, Jongil Hwang, Byung-Hun Min, Mun-Yang Park, Hyun-Kyu Yu:
1-5.6 Gb/s CMOS clock and data recovery IC with a static phase offset compensated linear phase detector. IET Circuits Devices Syst. 7(3) (2013)
2012
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Ja-Yol Lee, Mi-Jeong Park, Byung-Hun Min, Seongdo Kim, Mun-Yang Park, Hyun-Kyu Yu:
A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error Compensation. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(8): 1706-1719 (2012)
2011
[c1]
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  - conf/esscirc/NguyenJMLLEY11
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Hoai-Nam Nguyen, Seung-Hwan Jung, Byung-Hun Min, Young-Jae Lee, Sang-Gug Lee, Yun Seong Eo, Hyun-Kyu Yu:
A low power discrete-time receiver for triple-band FM/T-DMB/DAB system-on-chip. ESSCIRC 2011: 311-314

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