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2010 – 2019
- 2017
[c12]Haris Isakovic, Radu Grosu, Denise Ratasich, Jiri Kadlec, Zdenek Pohl, Steve Kerrison
, Kyriakos Georgiou, Kerstin Eder, Norbert Druml, Lillian Tadros, Flemming Christensen, Emilie Wheatley, Bastian Farkas, Rolf Meyer, Mladen Berekovic:
A Survey of Hardware Technologies for Mixed-Critical Integration Explored in the Project EMC^2. SAFECOMP Workshops 2017: 127-140- 2011
- [c11]Zdenek Pohl, Milan Tichý:
Resource Management for the Heterogeneous Arrays of Hardware Accelerators. FPL 2011: 486-489 - [c10]Michiel W. van Tol, Zdenek Pohl, Milan Tichý:
A Framework for Self-adaptive Collaborative Computing on Reconfigurable Platforms. PARCO 2011: 579-586
2000 – 2009
- 2008
- [j2]Zdenek Pohl, Milan Tichý, Jiri Kadlec:
Implementation of the Least-Squares Lattice with Order and Forgetting Factor Estimation for FPGA. EURASIP J. Adv. Signal Process. 2008 (2008) - [j1]John N. Coleman, Christopher I. Softley, Jiri Kadlec, Rudolf Matousek, Milan Tichý, Zdenek Pohl, Antonin Hermanek, Nico F. Benschop:
The European Logarithmic Microprocesor. IEEE Trans. Computers 57(4): 532-546 (2008) - 2007
- [c9]Zdenek Pohl, Milan Tichý:
RLS Lattice Algorithm with Order Probability Evaluation as an Accelerator for the Microblaze Processor. FPL 2007: 774-777 - 2005
- [c8]Kelly Nasi, Martin Danek, Theodoros Karoubalis, Zdenek Pohl:
Figaro: an automatic tool flow for designs with dynamic reconfiguration (abstract only). FPGA 2005: 262 - [c7]Kelly Nasi, Martin Danek, Theodoros Karoubalis, Zdenek Pohl:
Figaro - An Automatic Tool Flow for Designs with Dynamic Reconfiguration. FPL 2005: 590-593 - [c6]Zdenek Pohl, Premysl Sucha, Jiri Kadlec, Zdenek Hanzálek:
Performance Tuning of Iterative Algorithms in Signal Processing. FPL 2005: 699-702 - 2004
- [c5]Premysl Sucha, Zdenek Pohl, Zdenek Hanzálek:
Scheduling of Iterative Algorithms on FPGA with Pipelined Arithmetic Unit. IEEE Real-Time and Embedded Technology and Applications Symposium 2004: 404-412 - 2003
- [c4]Zdenek Pohl, Rudolf Matousek, Jiri Kadlec, Milan Tichý, Miroslav Lícko:
Lattice adaptive filter implementation for FPGA. FPGA 2003: 246 - [c3]Antonin Hermanek, Zdenek Pohl, Jiri Kadlec:
FPGA Implementation of the Adpaptive Lattice Filter. FPL 2003: 1095-1098 - [c2]Zdenek Pohl, Jan Schier, Miroslav Lícko, Antonin Hermanek, Milan Tichý, Rudolf Matousek, Jiri Kadlec:
Logarithmic Arithmetic for Real Data Types and Support for Matlab/Simulink Based Rapid-FPGA-Prototyping. IPDPS 2003: 190 - 2002
- [c1]Rudolf Matousek, Milan Tichý, Zdenek Pohl, Jiri Kadlec, Christopher I. Softley, Nick Coleman:
Logarithmic Number System and Floating-Point Arithmetics on FPGA. FPL 2002: 627-636
Coauthor Index
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