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ORCIDHailong Yao 0002
Person information
- affiliation: University of Science and Technology Beijing, School of Computer and Communication Engineering, Beijing, China
- affiliation (2009 - 2022): Tsinghua University, Department of Computer Science and Technology and Beijing National Research Center for Information Science and Technology, Beijing, China
- affiliation (2007 - 2009): University of California at San Diego, ECE Department, San Diego, CA, USA
- affiliation (PhD 2007): Tsinghua University, Department of Computer Science and Technology, Beijing, China
Other persons with the same name
- Hailong Yao
- Hailong Yao 0001
![[0000-0002-0638-8494]](https://dblp.dagstuhl.de/img/orcid-mark.12x12.png "0000-0002-0638-8494")
— Lanzhou City University, School of Information Engineering, Lanzhou, China - Hailong Yao 0003 — Zhengzhou University of Light Industry, Zhengzhou, China
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2020 – today
- 2025
[c53]Zhiyang Chen, Hailong Yao, Xia Yin:
PatLabor: Pareto Optimization of Timing-Driven Routing Trees. DAC 2025: 1-7- [c52]Mingyang Kou, Weiqing Ji, Shouyi Yin, Hailong Yao:
GPS: GNN-Based Two-Stage Pre-Scheduling Loop Mapping Method on CGRAs. DAC 2025: 1-7 - [c51]Chengkai Wang, Weiqing Ji, Mingyang Kou, Zhiyang Chen, Fei Li, Nengyong Zhu, Hailong Yao:
Mr.TPL: A Method for Multi-Pin Net Router in Triple Patterning Lithography. DAC 2025: 1-6 - [c50]Haochang Tian, Weiqing Ji, Mingyang Kou, Chengkai Wang, Fei Li, Hailong Yao:
VAER: Via-Aware Escape Routing for Chiplet Interconnection. ACM Great Lakes Symposium on VLSI 2025: 873-878 - [c49]Zhiyang Chen, Hailong Yao, Xia Yin:
Learning Configurations for Data-Driven Multi-Objective Optimization. ICML 2025 - 2024
- [j27]Weiqing Ji, Xingzhuo Guo, Shouan Pan, Fei Long, Tsung-Yi Ho, Ulf Schlichtmann, Hailong Yao:
GNN-Based Concentration Prediction With Variable Input Flow Rates for Microfluidic Mixers. IEEE Trans. Biomed. Circuits Syst. 18(3): 622-635 (2024) - [c48]Kenglun Chang, Jintian Ge, Hailong Yao, Yin Xia:
Supervised Contrastive Learning based Fine-tuning Framework with Small-Scale WSI Dataset on ViT. ICBBT 2024: 122-130 - [i2]Chengkai Wang, Weiqing Ji, Mingyang Kou, Zhiyang Chen, Fei Li, Hailong Yao:
Mr.TPL: A Method for Multi-Pin Net Router in Triple Patterning Lithography. CoRR abs/2412.02703 (2024) - 2023
- [j26]Mingyang Kou, Jiangyuan Gu, Hailong Yao, Shaojun Wei, Shouyi Yin:
TAEM 2.0: A Faster Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(8): 2552-2565 (2023) - [j25]Chen Jiang, Rongquan Yang, Qi Xu, Hailong Yao, Tsung-Yi Ho, Bo Yuan:
A Cooperative Multiagent Reinforcement Learning Framework for Droplet Routing in Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 3007-3020 (2023) - [c47]Jun Zeng, Panfeng Wang, Haili Wang, Hailong Yao, Fuchun Sun:
A Compilation Toolchain of Neural Networks for FPGA Backend. ASICON 2023: 1-4 - [c46]Weiqing Ji, Xingcheng Yao, Hailong Yao, Tsung-Yi Ho, Ulf Schlichtmann, Xia Yin:
SOAER: Self-Obstacle Avoiding Escape Routing for Paper-Based Digital Microfluidic Biochips. ACM Great Lakes Symposium on VLSI 2023: 255-260 - [c45]Weiqing Ji, Hailong Yao, Tsung-Yi Ho, Ulf Schlichtmann, Xia Yin:
GAT-based Concentration Prediction for Random Microfluidic Mixers with Multiple Input Flow Rates. ACM Great Lakes Symposium on VLSI 2023: 483-488 - [c44]Zhiyang Chen, Tsung-Yi Ho, Ulf Schlichtmann, Datao Chen, Mingyu Liu, Hailong Yao, Xia Yin:
NeuroEscape: Ordered Escape Routing via Monte-Carlo Tree Search and Neural Network. ICCAD 2023: 1-9 - 2022
- [j24]Hui-Chieh Yu, Yu-Huei Lin, Zhiyang Chen, Bing Li, Xing Huang, Ulf Schlichtmann, Tsung-Yi Ho, Hailong Yao:
Contamination-Aware Synthesis for Programmable Microfluidic Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 5016-5029 (2022) - [c43]Mingyang Kou, Jun Zeng, Boxiao Han, Fei Xu, Jiangyuan Gu, Hailong Yao:
GEML: GNN-based efficient mapping method for large loop applications on CGRA. DAC 2022: 337-342 - [c42]Weiqing Ji, Xingzhuo Guo, Shouan Pan, Tsung-Yi Ho, Ulf Schlichtmann, Hailong Yao:
GNN-based concentration prediction for random microfluidic mixers. DAC 2022: 763-768 - [c41]Jun Zeng, Mingyang Kou, Hailong Yao:
KunlunTVM: A Compilation Framework for Kunlun Chip Supporting Both Training and Inference. ACM Great Lakes Symposium on VLSI 2022: 299-304 - [c40]Kenglun Chang, Yanyuet Man, Hailong Yao:
A Semi-supervised Framework for Automatic Pixel-Wise Breast Cancer Grading of Histological Images. MICAD 2022: 53-65 - [c39]Jun Zeng, Mingyang Kou, Hailong Yao:
NeuroSchedule: A Novel Effective GNN-based Scheduling Method for High-level Synthesis. NeurIPS 2022 - 2021
- [j23]Chunfeng Liu, Xing Huang, Bing Li, Hailong Yao, Paul Pop, Tsung-Yi Ho, Ulf Schlichtmann:
DCSA: Distributed Channel-Storage Architecture for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(1): 115-128 (2021) - [j22]Mingyang Kou, Pei-Yi Cheng, Jun Zeng, Tsung-Yi Ho, Kazuyoshi Takagi, Hailong Yao:
Splitter-Aware Multiterminal Routing With Length-Matching Constraint for RSFQ Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(11): 2251-2264 (2021) - [c38]Wei Zhang, Yongxiao Zhou, Tsung-Yi Ho, Hailong Yao:
Concentration Gradients Enhancement of Christmas-Tree Structure Based on a Look-Up Table. ACM Great Lakes Symposium on VLSI 2021: 141-146 - [c37]Zhiyang Chen, Weiqing Ji, Yihao Peng, Datao Chen, Mingyu Liu, Hailong Yao:
Machine Learning Based Acceleration Method for Ordered Escape Routing. ACM Great Lakes Symposium on VLSI 2021: 365-370 - 2020
- [j21]Jiayi Weng, Tsung-Yi Ho, Weiqing Ji, Peng Liu, Mengdi Bao, Hailong Yao:
URBER: Ultrafast Rule-Based Escape Routing Method for Large-Scale Sample Delivery Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(1): 157-170 (2020) - [j20]Qin Wang, Ulf Schlichtmann, Yici Cai, Weiqing Ji, Zeyan Li, Haena Cheong, Oh-Sun Kwon, Hailong Yao, Tsung-Yi Ho, Kwanwoo Shin, Bing Li:
Integrated Control-Fluidic Codesign Methodology for Paper-Based Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(3): 613-625 (2020) - [j19]Ying Zhu, Xing Huang, Bing Li, Tsung-Yi Ho, Qin Wang, Hailong Yao, Robert Wille, Ulf Schlichtmann:
Multicontrol: Advanced Control-Logic Synthesis for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2489-2502 (2020) - [j18]Weiqing Ji, Tsung-Yi Ho, Junchao Wang, Hailong Yao:
Microfluidic Design for Concentration Gradient Generation Using Artificial Neural Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2544-2557 (2020) - [j17]Lingxuan Shao, Wentai Li, Tsung-Yi Ho, Sudip Roy, Hailong Yao:
Lookup Table-Based Fast Reliability-Aware Sample Preparation Using Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2708-2721 (2020) - [c36]Weiqing Ji, Tsung-Yi Ho, Hailong Yao:
Transfer Learning-Based Microfluidic Design System for Concentration Generation∗. DAC 2020: 1-6 - [c35]Mingyang Kou, Jiangyuan Gu, Shaojun Wei, Hailong Yao, Shouyi Yin:
TAEM: Fast Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA. DAC 2020: 1-6
2010 – 2019
- 2019
- [j16]Qinghang Zhao, Wenyu Sun, Jiaqing Zhao, Jian Zhao, Hailong Yao, Tsung-Yi Ho, Xiaojun Guo, Huazhong Yang, Yongpan Liu:
Design Methodology for TFT-Based Pseudo-CMOS Logic Array With Multilayer Interconnection Architecture and Optimization Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(11): 2043-2057 (2019) - [c34]Yanyuet Man, Hailong Yao:
Automatic Breast Cancer Grading of Histological Images using Dilated Residual Network. ICBBT 2019: 8-13 - 2018
- [j15]Qin Wang, Hao Zou, Hailong Yao, Tsung-Yi Ho, Robert Wille, Yici Cai:
Physical Co-Design of Flow and Control Layers for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1157-1170 (2018) - [j14]Kailin Yang, Hailong Yao, Tsung-Yi Ho, Kunze Xin, Yici Cai:
AARF: Any-Angle Routing for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(12): 3042-3055 (2018) - [j13]Hongxia Zhou, Chiu-Wing Sham, Hailong Yao:
Revisiting Routability-Driven Placement for Analog and Mixed-Signal Circuits. ACM Trans. Design Autom. Electr. Syst. 23(2): 17:1-17:17 (2018) - [c33]Ying Zhu, Bing Li, Tsung-Yi Ho, Qin Wang, Hailong Yao, Robert Wille, Ulf Schlichtmann:
Multi-channel and fault-tolerant control multiplexing for flow-based microfluidic biochips. ICCAD 2018: 123 - [c32]Weiqing Ji, Tsung-Yi Ho, Hailong Yao:
More Effective Randomly-Designed Microfluidics. ISVLSI 2018: 660-665 - [c31]Chun-Yu Lin, Juinn-Dar Huang, Hailong Yao, Tsung-Yi Ho:
A Comprehensive Security System for Digital Microfluidic Biochips. ITC-Asia 2018: 151-156 - 2017
- [j12]Qin Wang, Yue Xu, Shiliang Zuo, Hailong Yao, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann, Yici Cai:
Pressure-Aware Control Layer Optimization for Flow-Based Microfluidic Biochips. IEEE Trans. Biomed. Circuits Syst. 11(6): 1488-1499 (2017) - [c30]Qin Wang, Shiliang Zuo, Hailong Yao, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann, Yici Cai:
Hamming-distance-based valve-switching optimization for control-layer multiplexing in flow-based microfluidic biochips. ASP-DAC 2017: 524-529 - [c29]Andreas Grimmer, Qin Wang, Hailong Yao, Tsung-Yi Ho, Robert Wille:
Close-to-optimal placement and routing for continuous-flow microfluidic biochips. ASP-DAC 2017: 530-535 - [c28]Chunfeng Liu, Bing Li, Hailong Yao, Paul Pop, Tsung-Yi Ho, Ulf Schlichtmann:
Transport or Store?: Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage. DAC 2017: 49:1-49:6 - [c27]Qinghang Zhao, Yongpan Liu, Wenyu Sun, Jiaqing Zhao, Hailong Yao, Xiaojun Guo, Huazhong Yang:
Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture. DAC 2017: 80:1-80:6 - [c26]Lingxuan Shao, Yibin Yang, Hailong Yao, Tsung-Yi Ho, Yici Cai:
LUTOSAP: Lookup Table Based Online Sample Preparation in Microfluidic Biochips. ACM Great Lakes Symposium on VLSI 2017: 447-450 - [i1]Chunfeng Liu, Bing Li, Hailong Yao, Paul Pop, Tsung-Yi Ho, Ulf Schlichtmann:
Transport or Store? Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage. CoRR abs/1705.04998 (2017) - 2016
- [j11]Hailong Yao, Qin Wang, Yiren Shen, Tsung-Yi Ho, Yici Cai:
Integrated Functional and Washing Routing Optimization for Cross-Contamination Removal in Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(8): 1283-1296 (2016) - [c25]Qin Wang, Yizhong Ru, Hailong Yao, Tsung-Yi Ho, Yici Cai:
Sequence-pair-based placement and routing for flow-based microfluidic biochips. ASP-DAC 2016: 587-592 - [c24]Qin Wang, Zeyan Li, Haena Cheong, Oh-Sun Kwon, Hailong Yao, Tsung-Yi Ho, Kwanwoo Shin, Bing Li, Ulf Schlichtmann, Yici Cai:
Control-fluidic CoDesign for paper-based digital microfluidic biochips. ICCAD 2016: 103 - 2015
- [j10]Hailong Yao, Qin Wang, Yizhong Ru, Yici Cai, Tsung-Yi Ho:
Integrated Flow-Control Codesign Methodology for Flow-Based Microfluidic Biochips. IEEE Des. Test 32(6): 60-68 (2015) - [j9]Hailong Yao, Fan Yang, Yici Cai, Qiang Zhou, Chiu-Wing Sham:
SIAR: Customized real-time interactive router for analog circuits. Integr. 48: 170-182 (2015) - [j8]Yici Cai, Chao Deng, Qiang Zhou, Hailong Yao, Feifei Niu, Cliff N. Sze:
Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion. IEEE Trans. Very Large Scale Integr. Syst. 23(1): 142-155 (2015) - [c23]Hailong Yao, Tsung-Yi Ho, Yici Cai:
PACOR: practical control-layer routing flow with length-matching constraint for flow-based microfluidic biochips. DAC 2015: 142:1-142:6 - [c22]Qin Wang, Weiran He, Hailong Yao, Tsung-Yi Ho, Yici Cai:
SVM-Based Routability-Driven Chip-Level Design for Voltage-Aware Pin-Constrained EWOD Chips. ISPD 2015: 49-56 - 2014
- [j7]Wei Zhao, Hailong Yao, Yici Cai, Subarna Sinha, Charles C. Chiang:
Fast and scalable parallel layout decomposition in double patterning lithography. Integr. 47(2): 175-183 (2014) - [j6]Hailong Yao, Qiang Gao, Yici Cai, Qiang Zhou, Chiu-Wing Sham:
Length matching in detailed routing for analog and mixed signal circuits. Microelectron. J. 45(6): 604-612 (2014) - [c21]Qin Wang, Yiren Shen, Hailong Yao, Tsung-Yi Ho, Yici Cai:
Practical Functional and Washing Droplet Routing for Cross-Contamination Avoidance in Digital Microfluidic Biochips. DAC 2014: 143:1-143:6 - [c20]Hongxia Zhou, Chiu-Wing Sham, Hailong Yao:
Slicing Floorplans with Handling Symmetry and General Placement Constraints. ISVLSI 2014: 112-117 - 2013
- [c19]Weijie Chen, Hailong Yao, Yici Cai, Qiang Zhou:
Analog routing considering min-area constraint. ASICON 2013: 1-4 - [c18]Jinming Zhao, Hailong Yao, Yici Cai, Qiang Zhou:
A new splitting graph construction algorithm for SIAR router. ASICON 2013: 1-4 - [c17]Zihao Chen, Hailong Yao, Yici Cai:
SUALD: Spacing uniformity-aware layout decomposition in triple patterning lithography. ISQED 2013: 566-571 - 2012
- [c16]Hailong Yao, Yici Cai, Qiang Gao:
LEMAR: A novel length matching routing algorithm for analog and mixed signal circuits. ASP-DAC 2012: 157-162 - 2011
- [c15]Feifei Niu, Qiang Zhou, Hailong Yao, Yici Cai, Jianlei Yang, Chin Ngai Sze:
Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization. ACM Great Lakes Symposium on VLSI 2011: 199-204 - [c14]Fan Yang, Hailong Yao, Qiang Zhou, Yici Cai:
SIAR: splitting-graph-based interactive analog router. ACM Great Lakes Symposium on VLSI 2011: 367-370 - [c13]Qiang Gao, Hailong Yao, Qiang Zhou, Yici Cai:
A novel detailed routing algorithm with exact matching constraint for analog and mixed signal circuits. ISQED 2011: 36-41 - [c12]Zhongdong Qi, Qiang Zhou, Yanming Jia, Yici Cai, Zhuoyuan Li, Hailong Yao:
A novel fine-grain track routing approach for routability and crosstalk optimization. ISQED 2011: 621-626 - [c11]Shuzhe Zhou, Hailong Yao, Qiang Zhou, Yici Cai:
Minimization of Circuit Delay and Power through Gate Sizing and Threshold Voltage Assignment. ISVLSI 2011: 212-217 - 2010
- [j5]Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Yao:
Layout Decomposition Approaches for Double Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(6): 939-952 (2010) - [j4]Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao:
Dose Map and Placement Co-Optimization for Improved Timing Yield and Leakage Power. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(7): 1070-1082 (2010) - [c10]Qiang Gao, Yin Shen, Yici Cai, Hailong Yao:
Analog circuit shielding routing algorithm based on net classification. ISLPED 2010: 123-128
2000 – 2009
- 2009
- [c9]Kwangok Jeong, Andrew B. Kahng, Hailong Yao:
Revisiting the linear programming framework for leakage power vs. performance optimization. ISQED 2009: 127-134 - 2008
- [j3]Hailong Yao, Subarna Sinha, Jingyu Xu, Charles C. Chiang, Yici Cai, Xianlong Hong:
Efficient range pattern matching algorithm for process-hotspot detection. IET Circuits Devices Syst. 2(1): 2-15 (2008) - [c8]Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao:
Dose map and placement co-optimization for timing yield enhancement and leakage power reduction. DAC 2008: 516-521 - [c7]Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Yao:
Layout decomposition for double patterning lithography. ICCAD 2008: 465-472 - 2007
- [c6]Hailong Yao, Yici Cai, Xianlong Hong:
CMP-aware Maze Routing Algorithm for Yield Enhancement. ISVLSI 2007: 239-244 - 2006
- [j2]Hailong Yao, Yici Cai, Qiang Zhou, Xianlong Hong:
Multilevel Routing With Redundant Via Insertion. IEEE Trans. Circuits Syst. II Express Briefs 53-II(10): 1148-1152 (2006) - [c5]Xianlong Hong, Yici Cai, Hailong Yao, Duo Li:
DFM-aware Routing for Yield Enhancement. APCCAS 2006: 1091-1094 - [c4]Hailong Yao, Subarna Sinha, Charles C. Chiang, Xianlong Hong, Yici Cai:
Efficient process-hotspot detection using range pattern matching. ICCAD 2006: 625-632 - [c3]Hailong Yao, Yici Cai, Xianlong Hong:
Congestion-driven W-shape multilevel full-chip routing framework. ISCAS 2006 - 2005
- [j1]Hailong Yao, Yici Cai, Qiang Zhou, Xianlong Hong:
Crosstalk-Aware Routing Resource Assignment. J. Comput. Sci. Technol. 20(2): 231-236 (2005) - [c2]Hailong Yao, Yici Cai, Xianlong Hong, Qiang Zhou:
Improved multilevel routing with redundant via placement for yield and reliability. ACM Great Lakes Symposium on VLSI 2005: 143-146 - 2004
- [c1]Hailong Yao, Qiang Zhou, Xianlong Hong, Yici Cai:
Crosstalk driven routing resource assignment. ISCAS (5) 2004: 89-92
Coauthor Index
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