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Dian Zhou
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2020 – today
- 2024
- [j71]Dian Zhou, Shiguang Liu
, Qing Xu:
Music conditioned 2D hand gesture dance generation with HGS. Comput. Animat. Virtual Worlds 35(1) (2024) - [j70]Tianchen Gu
, Wangzhen Li
, Aidong Zhao, Zhaori Bi
, Xudong Li, Fan Yang
, Changhao Yan
, Wenchuang Walter Hu, Dian Zhou
, Tao Cui
, Xin Liu
, Zaikun Zhang, Xuan Zeng
:
BBGP-sDFO: Batch Bayesian and Gaussian Process Enhanced Subspace Derivative Free Optimization for High-Dimensional Analog Circuit Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(2): 417-430 (2024) - [j69]Zhaoting Chen
, Junzhe Cai
, Changhao Yan
, Zhaori Bi
, Yuzhe Ma
, Bei Yu
, Wenchuang Walter Hu, Dian Zhou
, Xuan Zeng
:
pNeurFill: Enhanced Neural Network Model-Based Dummy Filling Synthesis With Perimeter Adjustment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(2): 667-680 (2024) - [j68]Aidong Zhao
, Tianchen Gu
, Zhaori Bi
, Fan Yang
, Changhao Yan
, Xuan Zeng
, Zixiao Lin
, Wenchuang Walter Hu, Dian Zhou
:
D3PBO: Dynamic Domain Decomposition-based Parallel Bayesian Optimization for Large-scale Analog Circuit Sizing. ACM Trans. Design Autom. Electr. Syst. 29(3): 44:1-44:25 (2024) - [c124]Ruiyu Lyu, Yuan Meng, Aidong Zhao, Zhaori Bi, Keren Zhu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
A Study on Exploring and Exploiting the High-dimensional Design Space for Analog Circuit Design Automation : (Invited Paper). ASPDAC 2024: 671-678 - [c123]Xuyang Zhao, Zhaori Bi, Changhao Yan, Fan Yang, Ye Lu, Dian Zhou, Xuan Zeng:
Asynchronous Batch Constrained Multi-Objective Bayesian Optimization for Analog Circuit Sizing. ASPDAC 2024: 872-877 - [c122]Yuan Meng, Ruiyu Lyu, Zhaori Bi, Changhao Yan, Fan Yang, Wenchuang Hu, Dian Zhou, Xuan Zeng:
Circuits Physics Constrained Predictor of Static IR Drop with Limited Data. DATE 2024: 1-2 - 2023
- [j67]Guanghui Zheng
, Yan Wang, Chengyi Zhao, Wen Dai
, Giri Raj Kattel
, Dian Zhou:
Quantitative Analysis of Tidal Creek Evolution and Vegetation Variation in Silting Muddy Flats on the Yellow Sea. Remote. Sens. 15(21): 5107 (2023) - [j66]Qingxue Zhang, Dian Zhou:
Machine Learning Electrocardiogram for Mobile Cardiac Pattern Extraction. Sensors 23(12): 5723 (2023) - [j65]Aosheng Wang
, Guanghui Zheng
, Danping Wei, Caixia Jiao, Xianli Xie, Rong Zeng, Chengyi Zhao, Giri Kattel
, Ying Xiong, Dian Zhou
:
Identification and Evolution of Soil Organic Carbon Density Caused by Coastal Rapid Siltation Based on Imaging Spectroscopy. IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens. 16: 4287-4300 (2023) - [j64]Biao He
, Shuhan Zhang, Yifan Wang
, Tianning Gao
, Fan Yang
, Changhao Yan
, Dian Zhou
, Zhaori Bi
, Xuan Zeng
:
A Batched Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-Fidelity Modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(2): 347-359 (2023) - [j63]Jiangli Huang
, Chuyu Wang, Yuyang Yan, Cong Tao
, Fan Yang
, Changhao Yan
, Wenchuang Walter Hu, Dian Zhou
, Xuan Zeng
:
An Analog Circuit Building Block Generator via Nested Multi-Fidelity Modeling. IEEE Trans. Circuits Syst. I Regul. Pap. 70(8): 3280-3293 (2023) - [c121]Aidong Zhao, Xianan Wang, Zixiao Lin, Zhaori Bi
, Xudong Li, Changhao Yan, Fan Yang, Li Shang, Dian Zhou, Xuan Zeng:
cVTS: A Constrained Voronoi Tree Search Method for High Dimensional Analog Circuit Synthesis. DAC 2023: 1-6 - 2022
- [j62]Yan Qiu, Shuai Ding, Di Tian, Caiyun Zhang, Dian Zhou:
Predicting the quality of answers with less bias in online health question answering communities. Inf. Process. Manag. 59(6): 103112 (2022) - [j61]Shuhan Zhang
, Fan Yang
, Changhao Yan
, Dian Zhou
, Xuan Zeng
:
An Efficient Batch-Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multiobjective Acquisition Ensemble. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(1): 1-14 (2022) - [j60]Zhengqi Gao
, Jun Tao
, Yangfeng Su, Dian Zhou
, Xuan Zeng
, Xin Li:
Fast Statistical Analysis of Rare Failure Events With Truncated Normal Distribution in High-Dimensional Variation Space. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 789-793 (2022) - [j59]Jun Tao
, Handi Yu, Yangfeng Su, Dian Zhou
, Xuan Zeng
, Xin Li:
Correlated Rare Failure Analysis via Asymptotic Probability Evaluation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(4): 813-826 (2022) - [j58]Xiaodong Wang
, Changhao Yan
, Yuzhe Ma
, Bei Yu
, Fan Yang
, Dian Zhou
, Xuan Zeng
:
Analog Circuit Yield Optimization via Freeze-Thaw Bayesian Optimization Technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4887-4900 (2022) - [j57]Yifan Wang
, Zhaori Bi
, Yuxue Xie, Tao Wu, Xuan Zeng
, Shuang Chen, Dian Zhou
:
Learning From Highly Confident Samples for Automatic Knee Osteoarthritis Severity Assessment: Data From the Osteoarthritis Initiative. IEEE J. Biomed. Health Informatics 26(3): 1239-1250 (2022) - [j56]Yiyang Jiang
, Fan Yang
, Bei Yu
, Dian Zhou
, Xuan Zeng
:
Efficient Layout Hotspot Detection via Neural Architecture Search. ACM Trans. Design Autom. Electr. Syst. 27(6): 62:1-62:16 (2022) - [c120]Jingyao Zhao, Changhao Yan, Zhaori Bi, Fan Yang, Xuan Zeng, Dian Zhou:
A Novel and Efficient Bayesian Optimization Approach for Analog Designs with Multi-Testbench. ASP-DAC 2022: 86-91 - [c119]Xiaodong Wang, Changhao Yan, Fan Yang, Dian Zhou, Xuan Zeng:
An efficient yield optimization method for analog circuits via gaussian process classification and varying-sigma sampling. DAC 2022: 625-630 - [c118]Longlong Yang, Cuiyang Ding, Changhao Yan, Dian Zhou, Xuan Zeng:
A High-Precision Stochastic Solver for Steady-State Thermal Analysis with Fourier Heat Transfer Robin Boundary Conditions. ICCAD 2022: 50:1-50:9 - [c117]Xu Fu, Changhao Yan, Zhaori Bi, Fan Yang, Dian Zhou, Xuan Zeng:
A Batch Bayesian Optimization Approach For Analog Circuit Synthesis Based On Multi-Points Selection Criterion. ISCAS 2022: 2886-2890 - [c116]Shuhan Zhang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
LinEasyBO: Scalable Bayesian Optimization Approach for Analog Circuit Synthesis via One-Dimensional Subspaces. MLCAD 2022: 27-34 - 2021
- [j55]Qingxue Zhang
, Vincenzo Piuri, Edward A. Clancy, Dian Zhou, Thomas Penzel
, Wenchuang Walter Hu:
IEEE Access Special Section Editorial: Advanced Information Sensing and Learning Technologies for Data-Centric Smart Health Applications. IEEE Access 9: 30404-30407 (2021) - [j54]Qingxue Zhang
, Vincenzo Piuri, Edward A. Clancy, Dian Zhou, Thomas Penzel
, Wenchuang Walter Hu, Hui Zheng:
IEEE Access Special Section Editorial: Smart Health Sensing and Computational Intelligence: From Big Data to Big Impacts. IEEE Access 9: 30452-30455 (2021) - [j53]Yiyang Jiang
, Fan Yang
, Bei Yu
, Dian Zhou, Xuan Zeng
:
Efficient Layout Hotspot Detection via Binarized Residual Neural Network Ensemble. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(7): 1476-1488 (2021) - [c115]Jiahui Hu, Changhao Yan, Chao Guo, Ronggui Jiang, Dian Zhou, Xuan Zeng:
A Fast Aging-aware Static Timing Analysis Prediction Frame of Digital Integrated Circuits. ASICON 2021: 1-4 - [c114]Yan Wang, Changhao Yan, Dian Zhou, Xuan Zeng:
High-Dimensional Bayesian Optimization for Automated Analog Circuit Design via Add-Graph Structure. ASICON 2021: 1-4 - [c113]Jiangli Huang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization. ASP-DAC 2021: 146-151 - [c112]Zhengqi Gao, Zihao Chen, Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng:
Bayesian Inference on Introduced General Region: An Efficient Parametric Yield Estimation Method for Integrated Circuits. ASP-DAC 2021: 892-897 - [c111]Junzhe Cai, Changhao Yan, Yuzhe Ma, Bei Yu, Dian Zhou, Xuan Zeng:
NeurFill: Migrating Full-Chip CMP Simulators to Neural Networks for Model-Based Dummy Filling Synthesis. DAC 2021: 187-192 - [c110]Yue Shen, Changhao Yan, Sheng-Guo Wang, Dian Zhou, Xuan Zeng:
An Efficient Yield Estimation Method for Layouts of High Dimensional and High Sigma SRAM Arrays. DATE 2021: 1723-1728 - [c109]Jiangli Huang, Shuhan Zhang
, Cong Tao, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
Bayesian Optimization Approach for Analog Circuit Design Using Multi-Task Gaussian Process. ISCAS 2021: 1-5 - [i7]Dario Dematties, Chenyu Wen, Mauricio David Pérez, Dian Zhou, Shi-Li Zhang:
Deep learning of nanopore sensing signals using a bi-path network. CoRR abs/2105.03660 (2021) - [i6]Shuhan Zhang, Fan Yang, Dian Zhou, Xuan Zeng:
An Efficient Asynchronous Batch Bayesian Optimization Approach for Analog Circuit Synthesis. CoRR abs/2106.14683 (2021) - [i5]Shuhan Zhang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
An Efficient Batch Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-objective Acquisition Ensemble. CoRR abs/2106.15412 (2021) - [i4]Shuhan Zhang
, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
LinEasyBO: Scalable Bayesian Optimization Approach for Analog Circuit Synthesis via One-Dimensional Subspaces. CoRR abs/2109.00617 (2021) - 2020
- [j52]Mingchao Du
, Min Tao
, Jian Hong
, Dian Zhou
, Shuihua Wang
:
Application of Deep Learning Algorithm in Feature Mining and Rapid Identification of Colorectal Image. IEEE Access 8: 128830-128844 (2020) - [j51]Yiyang Jiang, Fan Yang, Hengliang Zhu, Dian Zhou, Xuan Zeng:
Nonlinear CNN: improving CNNs with quadratic convolutions. Neural Comput. Appl. 32(12): 8507-8516 (2020) - [j50]Zhengqi Gao
, Jun Tao
, Yangfeng Su, Dian Zhou, Xuan Zeng
, Xin Li
:
Efficient Rare Failure Analysis Over Multiple Corners via Correlated Bayesian Inference. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2029-2041 (2020) - [j49]Zhengqi Gao
, Jun Tao
, Dian Zhou, Xuan Zeng
:
Efficient Parametric Yield Estimation Over Multiple Process Corners via Bayesian Inference Based on Bernoulli Distribution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 3144-3148 (2020) - [j48]Fulin Peng, Handi Yu, Jun Tao
, Yangfeng Su, Dian Zhou, Xuan Zeng
, Xin Li
:
Efficient Statistical Analysis for Correlated Rare Failure Events via Asymptotic Probability Approximation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4971-4984 (2020) - [j47]Renjian Pan, Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng, Xin Li:
Analog/RF Post-silicon Tuning via Bayesian Optimization. ACM Trans. Design Autom. Electr. Syst. 25(1): 7:1-7:17 (2020) - [c108]Shuhan Zhang
, Fan Yang, Dian Zhou, Xuan Zeng:
Bayesian Methods for the Yield Optimization of Analog and SRAM Circuits. ASP-DAC 2020: 440-445 - [c107]Xiaodong Wang, Tianchen Gu, Changhao Yan, Xiulong Wu, Fan Yang, Sheng-Guo Wang, Dian Zhou, Xuan Zeng:
An Efficient and Robust Yield Optimization Method for High-dimensional SRAM Circuits. DAC 2020: 1-6 - [c106]Shuhan Zhang
, Fan Yang, Dian Zhou, Xuan Zeng:
An Efficient Asynchronous Batch Bayesian Optimization Approach for Analog Circuit Synthesis. DAC 2020: 1-6 - [c105]Biao He, Shuhan Zhang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
An Efficient Bayesian Optimization Approach for Analog Circuit Synthesis via Sparse Gaussian Process Modeling. DATE 2020: 67-72 - [c104]Zhibin Zhang, Dian Zhou, Jiqing Rao, Dongdong Zhao, Wenhua Hu, Jianwen Xiang, Zhongjin Liu, Yanzhen Xing:
VSFBS: Vulnerability Search in Firmware Based on String. DSA 2020: 555-563 - [c103]Binbin Liu, Fan Yang, Dian Zhou, Xuan Zeng:
An Efficient Memory Partitioning Approach for Multi-Pattern Data Access in STT-RAM. ISCAS 2020: 1-4 - [c102]Jialin Lu, Shuhan Zhang
, Fan Yang, Dian Zhou, Xuan Zeng:
A Mixed-Variable Bayesian Optimization Approach for Analog Circuit Synthesis. ISCAS 2020: 1-4 - [c101]Jiahe Shi
, Zhengqi Gao, Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng:
Multi-Corner Parametric Yield Estimation via Bayesian Inference on Bernoulli Distribution with Conjugate Prior. ISCAS 2020: 1-4 - [c100]Weijing Wen, Fan Yang, Yangfeng Su, Dian Zhou, Xuan Zeng:
Learning Low-Rank Structured Sparsity in Recurrent Neural Networks. ISCAS 2020: 1-4 - [i3]Zhengqi Gao, Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng:
Projection based Active Gaussian Process Regression for Pareto Front Modeling. CoRR abs/2001.07072 (2020)
2010 – 2019
- 2019
- [j46]Jun Tao
, Yangfeng Su, Dian Zhou, Xuan Zeng
, Xin Li
:
Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP Relaxation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(8): 1385-1398 (2019) - [j45]Wensong Li, Fan Yang, Hengliang Zhu, Xuan Zeng, Dian Zhou:
An Efficient Memory Partitioning Approach for Multi-Pattern Data Access via Data Reuse. ACM Trans. Reconfigurable Technol. Syst. 12(1): 1:1-1:22 (2019) - [j44]Xiang Ge
, Fan Yang
, Hengliang Zhu
, Xuan Zeng
, Dian Zhou:
An Efficient FPGA Implementation of Orthogonal Matching Pursuit With Square-Root-Free QR Decomposition. IEEE Trans. Very Large Scale Integr. Syst. 27(3): 611-623 (2019) - [c99]Huaidong Gao, Fan Yang, Dian Zhou, Xuan Zeng:
Parallel Global Placement on CPU via Parallel Reduction. ASICON 2019: 1-4 - [c98]Weijing Wen, Fan Yang, Yangfeng Su, Dian Zhou, Xuan Zeng:
Learning Sparse Patterns in Deep Neural Networks. ASICON 2019: 1-4 - [c97]Shuhan Zhang
, Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng, Xiangdong Hu:
An Efficient Multi-fidelity Bayesian Optimization Approach for Analog Circuit Synthesis. DAC 2019: 64 - [c96]Yiyang Jiang, Fan Yang, Hengliang Zhu, Bei Yu, Dian Zhou, Xuan Zeng:
Efficient Layout Hotspot Detection via Binarized Residual Neural Network. DAC 2019: 147 - [c95]Xin Wei, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng:
An Efficient FPGA-based Floating Random Walk Solver for Capacitance Extraction using SDAccel. DATE 2019: 1040-1045 - [c94]Shuhan Zhang
, Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network. DATE 2019: 1463-1468 - [c93]Mushuai Han, Dongdong Zhao, Hong Lin, Dian Zhou, Jianwen Xiang, Zhongjin Liu, Yanzhen Xing:
VSkLCG A Method for Cross-Platform Vulnerability Search in Firmware. DSA 2019: 395-400 - [c92]Zhengqi Gao, Jun Tao, Fan Yang, Yangfeng Su, Dian Zhou, Xuan Zeng:
Efficient Performance Trade-off Modeling for Analog Circuit based on Bayesian Neural Network. ICCAD 2019: 1-8 - [c91]Man Yu, Dongdong Zhao, Dian Zhou, Linjun Ran, Jianwen Xiang, Zhongjin Liu, Yanzhen Xing:
Vulnerability Detection in Firmware Based on Clonal Selection Algorithm. SSCI 2019: 1915-1921 - [i2]Shuhan Zhang, Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng, Xiangdong Hu:
An Efficient Multi-fidelity Bayesian Optimization Approach for Analog Circuit Synthesis. CoRR abs/1912.00392 (2019) - [i1]Shuhan Zhang, Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network. CoRR abs/1912.00402 (2019) - 2018
- [j43]Qingxue Zhang, Dian Zhou, Xuan Zeng:
A novel single-arm-worn 24 h heart disease monitor empowered by machine intelligence. Biomed. Signal Process. Control. 42: 129-133 (2018) - [j42]Yishi Yang, Hengliang Zhu
, Zhaori Bi, Changhao Yan, Dian Zhou, Yangfeng Su, Xuan Zeng:
Smart-MSP: A Self-Adaptive Multiple Starting Point Optimization Approach for Analog Circuit Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(3): 531-544 (2018) - [j41]Hengliang Zhu
, Feng Hu, Hao Zhou, David Z. Pan
, Dian Zhou, Xuan Zeng:
Interlayer Cooling Network Design for High-Performance 3D ICs Using Channel Patterning and Pruning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(4): 770-781 (2018) - [j40]Mengshuo Wang, Wenlong Lv, Fan Yang, Changhao Yan, Wei Cai, Dian Zhou, Xuan Zeng:
Efficient Yield Optimization for Analog and SRAM Circuits via Gaussian Process Regression and Adaptive Yield Estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10): 1929-1942 (2018) - [j39]Wenlong Lyu
, Pan Xue, Fan Yang
, Changhao Yan, Zhiliang Hong, Xuan Zeng
, Dian Zhou:
An Efficient Bayesian Optimization Approach for Automated Optimization of Analog Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(6): 1954-1967 (2018) - [j38]Jinyuan Zhai, Changhao Yan, Sheng-Guo Wang, Dian Zhou, Hai Zhou, Xuan Zeng:
An Efficient Non-Gaussian Sampling Method for High Sigma SRAM Yield Analysis. ACM Trans. Design Autom. Electr. Syst. 23(3): 36:1-36:23 (2018) - [j37]Hao Zhou
, Hengliang Zhu
, Tao Cui, David Z. Pan
, Dian Zhou, Xuan Zeng
:
Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs With a Novel Adaptive Strategy Finite Element Method. IEEE Trans. Very Large Scale Integr. Syst. 26(7): 1312-1325 (2018) - [j36]Ye Zhang
, Wenlong Lyu
, Wai-Shing Luk, Fan Yang
, Hai Zhou, Dian Zhou, David Z. Pan
, Xuan Zeng
:
Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization. IEEE Trans. Very Large Scale Integr. Syst. 26(9): 1613-1626 (2018) - [c90]Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
Multi-objective bayesian optimization for analog/RF circuit synthesis. DAC 2018: 11:1-11:6 - [c89]Fulin Peng, Changhao Yan, Chunyang Feng, Jianquan Zheng, Sheng-Guo Wang, Dian Zhou, Xuan Zeng:
A general graph based pessimism reduction framework for design optimization of timing closure. DAC 2018: 25:1-25:6 - [c88]Jinyuan Zhai, Changhao Yan, Sheng-Guo Wang, Dian Zhou:
An efficient Bayesian yield estimation method for high dimensional and high sigma SRAM circuits. DAC 2018: 132:1-132:6 - [c87]Wensong Li, Fan Yang, Hengliang Zhu, Xuan Zeng, Dian Zhou:
An efficient data reuse strategy for multi-pattern data access. ICCAD 2018: 118 - [c86]Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
Batch Bayesian Optimization via Multi-objective Acquisition Ensemble for Automated Analog Circuit Design. ICML 2018: 3312-3320 - 2017
- [j35]Qingxue Zhang
, Xuan Zeng, Wenchuang Walter Hu, Dian Zhou:
A Machine Learning-Empowered System for Long-Term Motion-Tolerant Wearable Monitoring of Blood Pressure and Heart Rate With Ear-ECG/PPG. IEEE Access 5: 10547-10561 (2017) - [j34]Qingxue Zhang
, Dian Zhou, Xuan Zeng:
HeartID: A Multiresolution Convolutional Neural Network for ECG-Based Biometric Human Identification in Smart Health Applications. IEEE Access 5: 11805-11816 (2017) - [j33]Guanming Huang, Donesh Gillin, Dian Zhou, Jin Liu, Xuan Zeng, Po-Yu Kuo:
An efficient and robust method to determine the optimal tap coefficients of high speed FIR equalizer. Sci. China Inf. Sci. 60(2): 22401 (2017) - [j32]Qingxue Zhang
, Dian Zhou, Xuan Zeng:
A Novel Framework for Motion-Tolerant Instantaneous Heart Rate Estimation by Phase-Domain Multiview Dynamic Time Warping. IEEE Trans. Biomed. Eng. 64(11): 2562-2574 (2017) - [j31]Wei Zeng, Hengliang Zhu
, Xuan Zeng, Dian Zhou, Ruey-Wen Liu, Xin Li:
C-YES: An Efficient Parametric Yield Estimation Approach for Analog and Mixed-Signal Circuits Based on Multicorner-Multiperformance Correlations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(6): 899-912 (2017) - [j30]Fan Yang
, Subarna Sinha, Charles C. Chiang, Xuan Zeng, Dian Zhou:
Improved Tangent Space-Based Distance Metric for Lithographic Hotspot Classification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(9): 1545-1556 (2017) - [j29]Jincheng Su
, Fan Yang
, Xuan Zeng, Dian Zhou, Jie Chen:
Efficient Memory Partitioning for Parallel Data Access in FPGA via Data Reuse. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(10): 1674-1687 (2017) - [j28]Zhaori Bi, Dian Zhou, Sheng-Guo Wang, Xuan Zeng:
Optimization and Quality Estimation of Circuit Design via Random Region Covering Method. ACM Trans. Design Autom. Electr. Syst. 23(1): 1:1-1:25 (2017) - [j27]Yunfeng Yang, Wai-Shing Luk, Hai Zhou, David Z. Pan, Dian Zhou, Changhao Yan, Xuan Zeng:
An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation. ACM Trans. Design Autom. Electr. Syst. 23(1): 11:1-11:27 (2017) - [j26]Mengshuo Wang
, Changhao Yan, Xin Li, Dian Zhou, Xuan Zeng
:
High-Dimensional and Multiple-Failure-Region Importance Sampling for SRAM Yield Analysis. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 806-819 (2017) - [c85]Ye Zhang, Wai-Shing Luk, Fan Yang, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng:
Network flow based cut redistribution and insertion for advanced 1D layout design. ASP-DAC 2017: 360-365 - [c84]Jiabei Ge, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng:
An efficient algorithm for stencil planning and optimization in E-beam lithography. ASP-DAC 2017: 366-371 - [c83]Jun Tao, Handi Yu, Dian Zhou, Yangfeng Su, Xuan Zeng, Xin Li:
Correlated Rare Failure Analysis via Asymptotic Probability Evaluation. DAC 2017: 54:1-54:6 - [c82]Wenlong Lv, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
Subgradient based multiple-starting-point algorithm for non-smooth optimization of analog circuits. DATE 2017: 1195-1200 - [c81]Chao Yan, Hengliang Zhu, Dian Zhou, Xuan Zeng:
An efficient leakage-aware thermal simulation approach for 3D-ICs using corrected linearized model and algebraic multigrid. DATE 2017: 1207-1212 - [c80]Fan Yang, Charles C. Chiang, Xuan Zeng, Dian Zhou:
Efficient SVM-based hotspot detection using spectral clustering. ISCAS 2017: 1-4 - [c79]Ye Zhang, Fan Yang, Dian Zhou, Xuan Zeng, Xiangdong Hu:
A grid-based detailed routing algorithm for advanced 1D process. ISCAS 2017: 1-4 - [c78]Shuhan Zhang
, Fan Yang, Xuan Zeng, Dian Zhou, Shun Li, Xiangdong Hu:
Efficient spectral graph sparsification via Krylov-subspace based spectral perturbation analysis. ISCAS 2017: 1-4 - [c77]Kun Lu, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng:
A Novel N-Retry Transactional Memory Model for Multi-Thread Programming. ISPA/IUCC 2017: 814-821 - [c76]Dian Zhou, Gang Zhang:
Study on mechanical properties of radial permanent magnet bearing. CIS/RAM 2017: 654-659 - [c75]Qingxue Zhang, Dian Zhou, Xuan Zeng:
Hear the heart: Daily cardiac health monitoring using Ear-ECG and machine learning. UEMCON 2017: 448-451 - [c74]Qingxue Zhang, Dian Zhou, Xuan Zeng:
PulsePrint: Single-arm-ECG biometric human identification using deep learning. UEMCON 2017: 452-456 - 2016
- [j25]Minghua Li, Guancheng Chen, Qijun Wang, Yonghua Lin, H. Peter Hofstee, Per Stenström, Dian Zhou:
PATer: A Hardware Prefetching Automatic Tuner on IBM POWER8 Processor. IEEE Comput. Archit. Lett. 15(1): 37-40 (2016) - [j24]Minghua Li, Guanming Huang, Xiulong Wu, Liuxi Qian, Xuan Zeng, Dian Zhou:
A yield-enhanced global optimization methodology for analog circuit based on extreme value theory. Sci. China Inf. Sci. 59(8): 082401:1-082401:16 (2016) - [j23]Changhai Liao, Jun Tao, Xuan Zeng, Yangfeng Su, Dian Zhou, Xin Li:
Efficient Spatial Variation Modeling of Nanoscale Integrated Circuits Via Hidden Markov Tree. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(6): 971-984 (2016) - [j22]Yunfeng Yang, Wai-Shing Luk, David Z. Pan, Hai Zhou, Changhao Yan, Dian Zhou, Xuan Zeng:
Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(9): 1532-1545 (2016) - [j21]Changhai Liao, Jun Tao, Handi Yu, Zhangwen Tang, Yangfeng Su, Dian Zhou, Xuan Zeng, Xin Li:
Efficient Hybrid Performance Modeling for Analog Circuits Using Hierarchical Shrinkage Priors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(12): 2148-2152 (2016) - [c73]Chenjie Yang, Fan Yang, Xuan Zeng, Dian Zhou:
An efficient trajectory-based algorithm for model order reduction of nonlinear systems via localized projection and global interpolation. ASP-DAC 2016: 551-556 - [c72]Qicheng Huang, Chenlei Fang, Fan Yang, Xuan Zeng, Dian Zhou, Xin Li:
Efficient performance modeling via Dual-Prior Bayesian Model Fusion for analog and mixed-signal circuits. DAC 2016: 8:1-8:6 - [c71]Chenlei Fang, Qicheng Huang, Fan Yang, Xuan Zeng, Dian Zhou, Xin Li:
Efficient performance modeling of analog integrated circuits via kernel density based sparse regression. DAC 2016: 10:1-10:6 - [c70]Changhai Liao, Jun Tao, Xuan Zeng, Yangfeng Su, Dian Zhou, Xin Li:
Efficient spatial variation modeling via robust dictionary learning. DATE 2016: 121-126 - [c69]Bo Peng, Fan Yang, Changhao Yan, Xuan Zeng, Dian Zhou:
Efficient multiple starting point optimization for automated analog circuit optimization via recycling simulation data. DATE 2016: 1417-1422 - [c68]Jincheng Su, Fan Yang, Xuan Zeng, Dian Zhou:
Efficient Memory Partitioning for Parallel Data Access via Data Reuse. FPGA 2016: 138-147 - [c67]Handi Yu, Jun Tao, Changhai Liao, Yangfeng Su, Dian Zhou, Xuan Zeng, Xin Li:
Efficient statistical analysis for correlated rare failure events via asymptotic probability approximation. ICCAD 2016: 18 - [c66]Zhelun Yu, Jincheng Su, Fan Yang, Yangfeng Su, Xuan Zeng, Dian Zhou, Weiping Shi:
Fast compressive sensing reconstruction algorithm on FPGA using Orthogonal Matching Pursuit. ISCAS 2016: 249-252 - [c65]Xuan Zeng, Chenlei Fang, Qicheng Huang, Fan Yang, Dian Zhou, Wei Cai, Weiping Shi:
High-speed link verification based on statistical inference. ISCAS 2016: 906-909 - 2015
- [j20]Liuxi Qian, Zhaori Bi, Dian Zhou, Xuan Zeng:
Automated Technology Migration Methodology for Mixed-Signal Circuit Based on Multistart Optimization Framework. IEEE Trans. Very Large Scale Integr. Syst. 23(11): 2595-2605 (2015) - [c64]Yunfeng Yang, Wai-Shing Luk, Hai Zhou, Changhao Yan, Xuan Zeng, Dian Zhou:
Layout decomposition co-optimization for hybrid e-beam and multiple patterning lithography. ASP-DAC 2015: 652-657 - [c63]Minghua Li, Zhaori Bi, Dian Zhou, Xuan Zeng:
Analog circuit performance bound estimation based on extreme value theory. MWSCAS 2015: 1-4 - 2013
- [j19]Guanming Huang, Liuxi Qian, Siwat Saibua, Dian Zhou, Xuan Zeng:
An Efficient Optimization Based Method to Evaluate the DRV of SRAM Cells. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(6): 1511-1520 (2013) - [j18]Wei Li, Dian Zhou, Minghua Li, Binh P. Nguyen, Xuan Zeng:
Near-Field Communication Transceiver System Modeling and Analysis Using SystemC/SystemC-AMS With the Consideration of Noise Issues. IEEE Trans. Very Large Scale Integr. Syst. 21(12): 2250-2261 (2013) - [c62]Zhaori Bi, Wei Li, Dian Zhou, Xuan Zeng, Sheng-Guo Wang:
Mixed-signal system verification by SystemC/SystemC-AMS and HSIM-VCS in near field communication tag design. ASICON 2013: 1-4 - [c61]Guanming Huang, Dian Zhou, Xuan Zeng, Shengguo Wang:
A practical method for auto-design and optimization of DC-DC buck converter. ASICON 2013: 1-4 - [c60]Minghua Li, Dian Zhou, Sheng-Guo Wang, Xuan Zeng:
FMSSQP: An efficient global optimization tool for the robust design of Rail-to-Rail Op-Amp. ASICON 2013: 1-4 - [c59]Liuxi Qian, Dian Zhou, Xuan Zeng, Shengguo Wang:
Oscillator phase noise verification accounting for process variations. ASICON 2013: 1-4 - [c58]Liuxi Qian, Dian Zhou, Xuan Zeng, Fan Yang, Shengguo Wang:
A parallel sparse linear system solver for large-scale circuit simulation based on Schur Complement. ASICON 2013: 1-4 - [c57]Dian Zhou, Guanming Huang:
Design automation of analog circuit considering the process variations. ASICON 2013: 1-4 - [c56]Haifeng Liu, Zheng Hu, Hui Tian, Dian Zhou:
An Adaptive Social Influence Propagation Model Based on Local Network Topology. EC-Web 2013: 14-26 - [c55]Haifeng Liu, Zheng Hu, Dian Zhou, Hui Tian:
Cumulative Probability Distribution Model for Evaluating User Behavior Prediction Algorithms. SocialCom 2013: 385-390 - 2012
- [j17]Huimin She, Zhonghai Lu, Axel Jantsch
, Dian Zhou, Li-Rong Zheng:
Performance Analysis of Flow-Based Traffic Splitting Strategy on Cluster-Mesh Sensor Networks. Int. J. Distributed Sens. Networks 8 (2012) - [j16]Po-Yu Kuo, Siwat Saibua, Guanming Huang, Dian Zhou:
An Efficient Method for Evaluating Analog Circuit Performance Bounds Under Process Variations. IEEE Trans. Circuits Syst. II Express Briefs 59-II(6): 351-355 (2012) - [c54]Tao Gong, Zheng Hu, Haifeng Liu, Feng Lin, Dian Zhou, Hui Tian:
A context-aware computing mediated dynamic service composition and reconfiguration for ubiquitous environment. IOT 2012: 16-23 - 2011
- [j15]Tracey Y. Zhou, Hang Liu, Dian Zhou, Tuna B. Tarim:
A Fast Analog Circuit Analysis Algorithm for Design Modification and Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(2): 308-313 (2011) - [c53]Liulin Zhong, Jiayi Sheng, Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng, Dian Zhou:
An optimized mapping algorithm based on Simulated Annealing for regular NoC architecture. ASICON 2011: 389-392 - [c52]Huimin She, Zhonghai Lu, Axel Jantsch
, Dian Zhou, Li-Rong Zheng:
Stochastic coverage in event-driven sensor networks. PIMRC 2011: 915-919 - [c51]Po-Yu Kuo, Siwat Saibua, Dian Zhou:
A novel approach to estimate the impact of analog circuit performance based on the small signal model under process variations. SoCC 2011: 70-75 - [c50]Siwat Saibua, Liuxi Qian, Dian Zhou:
Worst case analysis for evaluating VLSI circuit performance bounds using an optimization method. VLSI-SoC 2011: 102-105 - [c49]Huimin She, Zhonghai Lu, Axel Jantsch
, Dian Zhou, Li-Rong Zheng:
Modeling and analysis of Rayleigh fading channels using stochastic network calculus. WCNC 2011: 1056-1061 - 2010
- [j14]Shuang Zhao, Wenqing Lu, Xiaofang Zhou, Dian Zhou, Gerald E. Sobelman:
Implementations of FFT and STBD for MIMO-OFDM on a Reconfigurable Baseband Platform. IEICE Trans. Inf. Syst. 93-D(4): 811-821 (2010) - [j13]Jun Tao, Xuan Zeng, Wei Cai, Yangfeng Su, Dian Zhou:
Stochastic Sparse-Grid Collocation Algorithm for Steady-State Analysis of Nonlinear System with Process Variations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(6): 1204-1214 (2010) - [c48]Siwat Saibua, Po-Yu Kuo, Dian Zhou, Ming-e Jing:
A Folding Strategy for SAT solvers based on Shannon's expansion theorem. SoCC 2010: 177-181
2000 – 2009
- 2009
- [c47]Tracey Y. Zhou, Dian Zhou, Xuan Zeng:
Incremental Circuit Simulation Analysis for Design Modification and Verification. ISCAS 2009: 2753-2756 - [c46]Huimin She, Zhonghai Lu, Axel Jantsch
, Dian Zhou, Li-Rong Zheng:
Analytical Evaluation of Retransmission Schemes in Wireless Sensor Networks. VTC Spring 2009 - 2008
- [c45]Jian Chen, Fredrik Jonsson, Håkan K. Olsson, Li-Rong Zheng, Dian Zhou:
A current shaping technique to lower phase noise in LC oscillators. ICECS 2008: 392-395 - [c44]Shuang Zhao, Wenqing Lu, Chao Lu, Xiaofang Zhou, Dian Zhou, Gerald E. Sobelman:
An Efficient Multi-protocol RFID Interrogator Baseband Processor based on a Reconfigurable Architecture. ICESS 2008: 264-270 - [c43]Tracey Y. Zhou, Dian Zhou, Hua Zhang, Xinyue Niu:
Foundational-circuit-based spice simulation. ISCAS 2008: 876-879 - [c42]Peng Wang, Fredrik Jonsson, Dian Zhou, Lirong Zheng:
Low noise amplifier architecture analysis for UWB system. SoC 2008: 1-4 - [c41]Peng Wang, Hannu Tenhunen, Dian Zhou, Lirong Zheng:
PER performance enhancement through antenna and transceiver co-design for multi-band OFDM UWB communication. SoC 2008: 1-5 - 2007
- [j12]Ming-e Jing, Dian Zhou, Pushan Tang, Xiaofang Zhou, Hua Zhang:
Solving SAT problem by heuristic polarity decision-making algorithm. Sci. China Ser. F Inf. Sci. 50(6): 915-925 (2007) - [j11]Ming-e Jing, Yue Hao, Dian Zhou, Xuan Zeng:
A Novel Optimization Method for Parametric Yield: Uniform Design Mapping Distance Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(6): 1149-1155 (2007) - [c40]Jun Tao, Xuan Zeng, Wei Cai, Yangfeng Su, Dian Zhou, Charles C. Chiang:
Stochastic Sparse-grid Collocation Algorithm (SSCA) for Periodic Steady-State Analysis of Nonlinear System with Process Variations. ASP-DAC 2007: 474-479 - [c39]Hengliang Zhu, Xuan Zeng, Wei Cai, Jintao Xue, Dian Zhou:
A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology. DATE 2007: 1514-1519 - [c38]Huimin She, Zhonghai Lu, Axel Jantsch, Li-Rong Zheng, Dian Zhou:
Traffic Splitting with Network Calculus for Mesh Sensor Networks. FGCN (2) 2007: 368-373 - [c37]Fan Yang, Xuan Zeng, Yangfeng Su, Dian Zhou:
RLCSYN: RLC Equivalent Circuit Synthesis for Structure-Preserved Reduced-order Model of Interconnect. ISCAS 2007: 2710-2713 - 2006
- [j10]Wei Li, Daniel Blakely, Scott Van Sooy, Keven Dunn, David Kidd, Robert Rogenmoser, Dian Zhou:
LVS verification across multiple power domains for a quad-core microprocessor. ACM Trans. Design Autom. Electr. Syst. 11(2): 490-500 (2006) - [c36]Hengliang Zhu, Xuan Zeng, Wei Cai, Dian Zhou:
A Spectral Stochastic Collocation Method for Capacitance Extraction of Interconnects with Process Variations. APCCAS 2006: 1095-1098 - [c35]Xuan Zeng, Lihong Feng, Yangfeng Su, Wei Cai, Dian Zhou, Charles C. Chiang:
Time domain model order reduction by wavelet collocation method. DATE 2006: 21-26 - [c34]Jun Tao, Xuan Zeng, Fan Yang, Yangfeng Su, Lihong Feng, Wei Cai, Dian Zhou, Charles C. Chiang:
A one-shot projection method for interconnects with process variations. ISCAS 2006 - 2005
- [j9]Min Ding, Pushan Tang, Dian Zhou:
Integrating advanced reasoning into a SAT solver. Sci. China Ser. F Inf. Sci. 48(3): 366-378 (2005) - [j8]Dian Zhou, Ruiming Li:
Design and Verification of High-Speed VLSI Physical Design. J. Comput. Sci. Technol. 20(2): 147-165 (2005) - [j7]Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng:
Power-optimal simultaneous buffer insertion/sizing and wire sizing for two-pin nets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(12): 1915-1924 (2005) - [c33]Bang Liu, Xuan Zeng, Yangfeng Su, Jun Tao, Zhaojun Bai, Charles C. Chiang, Dian Zhou:
Block SAPOR: block Second-order Arnoldi method for Passive Order Reduction of multi-input multi-output RCS interconnect circuits. ASP-DAC 2005: 244-249 - [c32]Xuan Zeng, Bang Liu, Jun Tao, Charles C. Chiang, Dian Zhou:
A novel wavelet method for noise analysis of nonlinear circuits. ASP-DAC 2005: 471-476 - [c31]Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng:
Power-optimal simultaneous buffer insertion/sizing and uniform wire sizing for single long wires. ISCAS (1) 2005: 113-116 - [c30]Hua Zhang, Dian Zhou, Yi Hu, Ruiming Li, Jianzhong Zhang:
Phase noise spectra analysis for LC oscillators. ISCAS (3) 2005: 2263-2266 - 2004
- [c29]Jian Wang, Jun Tao, Xuan Zeng, Charles C. Chiang, Dian Zhou:
Analog circuit behavioral modeling via wavelet collocation method with auto-companding. ASP-DAC 2004: 45-50 - [c28]Ruiming Li, Dian Zhou, Donglei Du:
Satisfiability and integer programming as complementary tools. ASP-DAC 2004: 879-882 - [c27]Lihong Feng, Xuan Zeng, Charles C. Chiang, Dian Zhou, Qiang Fang:
Direct Nonlinear Order Reduction with Variational Analysis. DATE 2004: 1316-1321 - [c26]Xin Zhou, Dian Zhou, Jin Liu, Ruiming Li, Xuan Zeng, Charles C. Chiang:
Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method. DATE 2004: 1322-1326 - [c25]Yangfeng Su, Jian Wang, Xuan Zeng, Zhaojun Bai, Charles C. Chiang, Dian Zhou:
SAPOR: second-order Arnoldi method for passive order reduction of RCS circuits. ICCAD 2004: 74-79 - [c24]Nisar Ahmed, Mohammad H. Tehranipour, Dian Zhou, Mehrdad Nourani:
Frequency driven repeater insertion for deep submicron. ISCAS (5) 2004: 181-184 - [c23]Jian Wang, Xuan Zeng, Wei Cai, Charles C. Chiang, Jiarong Tong, Dian Zhou:
Frequency domain wavelet method with GMRES for large-scale linear circuit simulation. ISCAS (5) 2004: 321-324 - [c22]Hua Zhang, Jianzhong Zhang, Dian Zhou, Jin Liu, Liangjun Jiang, Yan Pan:
A closed-form phase noise solution for an ideal LC oscillator. ISCAS (4) 2004: 768-771 - [c21]Lihong Feng, Xuan Zeng, Jiarong Tong, Charles C. Chiang, Dian Zhou:
Two-sided projection method in variational equation model order reduction of nonlinear circuits. ISCAS (4) 2004: 816-819 - [c20]Ronald W. Mehler, Dian Zhou:
Automated Architectural Optimization of Digital FIR Filters. VLSI Design 2004: 177-182 - 2003
- [j6]Xin Li, Xuan Zeng, Dian Zhou, Xieting Ling, Wei Cai:
Behavioral modeling for analog system-level simulation by wavelet collocation method. IEEE Trans. Circuits Syst. II Express Briefs 50(6): 299-314 (2003) - [c19]Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng:
Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing. ICCAD 2003: 581-587 - [c18]Xuan Zeng, Jun Tao, Yangfeng Su, Wenbing Chen, Dian Zhou:
An error distribution based nonlinear companding method for analog behavioral modeling via wavelet approximation. ISCAS (3) 2003: 168-171 - [c17]Xuan Zeng, Sheng Huang, Yangfeng Su, Dian Zhou:
An efficient Sylvester equation solver for time domain circuit simulation by wavelet collocation method. ISCAS (4) 2003: 664-667 - 2002
- [c16]Yingtao Jiang, Yiyan Tang, Yuke Wang, Dian Zhou:
A DSP-based turbo codec for 3G communication systems. ICASSP 2002: 2685-2688 - [c15]Xin Li, Xuan Zeng, Dian Zhou, Xieting Ling:
Wavelet method for high-speed clock tree simulation. ISCAS (1) 2002: 177-180 - [c14]Ronald W. Mehler, Dian Zhou:
Architectural Synthesis of Finite Impulse Response Digital Filters. SBCCI 2002: 20-28 - 2001
- [c13]Xin Li, Xuan Zeng, Dian Zhou, Xieting Ling:
Behavioral Modeling of Analog Circuits by Wavelet Collocation Method. ICCAD 2001: 65-69 - [c12]Dian Zhou, Wei Li, Wei Cai, Nailong Guo:
An efficient balanced truncation realization algorithm for interconnect model order reduction. ISCAS (5) 2001: 383-386 - [c11]Wei Li, Dian Zhou, Haksu Kim, Xuan Zeng:
Automatic clock tree design with IPs in the system. ISCAS (5) 2001: 387-390 - 2000
- [j5]Xiaoyu Song, Qian-Yu Tang, Dian Zhou, Yuke Wang:
Wire space estimation and routability analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(5): 624-628 (2000) - [j4]Haksu Kim, Dian Zhou:
Efficient implementation of a planar clock routing with thetreatment of obstacles. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(10): 1220-1225 (2000) - [c10]Xuan Zeng, Mingyuan Li, Wenqing Zhao, Pushan Tang, Dian Zhou:
Parasitic and mismatch modeling for optimal stack generation [in CMOS]. ISCAS 2000: 193-196
1990 – 1999
- 1999
- [c9]Haksu Kim, Dian Zhou:
An automatic clock tree design system for high-speed VLSI designs: planar clock routing with the treatment of obstacles. ISCAS (6) 1999: 258-261 - [c8]Xuan Zeng, J. Guan, Wenqing Zhao, Pushan Tang, Dian Zhou:
A constraint-based placement refinement method for CMOS analog cell layout. ISCAS (6) 1999: 408-411 - [c7]Xuan Zeng, Dian Zhou, Wei Li:
Buffer insertion for clock delay and skew minimization. ISPD 1999: 36-41 - 1997
- [c6]Dian Zhou, Xingya Liu:
Minimization of chip size and power consumption of high-speed VLSI buffers. ISPD 1997: 186-191 - 1995
- [c5]Zhongli He, Dian Zhou:
Optimization of VLSI Allocation. ISCAS 1995: 1065-1068 - 1994
- [j3]Si-Qing Zheng, Dian Zhou:
Preface. VLSI Design 2(2): i (1994) - 1993
- [c4]Jason Cong, Kwok-Shing Leung, Dian Zhou:
Performance-Driven Interconnect Design Based on Distributed RC Delay Model. DAC 1993: 606-611 - [c3]Dian Zhou, F. Tsui:
Neighbour State Transition Method for VLSI Optimization Problems. ICCD 1993: 476-479 - [c2]D. S. Gao, Dian Zhou:
Propagation Delay in RLC Interconnection Networks. ISCAS 1993: 2125-2128 - [c1]Dian Zhou, S. Su, F. Tsui, D. S. Gao, Jason Cong:
A Two-pole Circuit Model for VLSI High-speed Interconnection. ISCAS 1993: 2129-2132 - 1990
- [b1]Dian Zhou:
Algorithms for VLSI routing. University of Illinois Urbana-Champaign, USA, 1990 - [j2]Dian Zhou:
An optimum channel routing algorithm in the restricted wire overlap model. Integr. 9(2): 163-177 (1990)
1980 – 1989
- 1989
- [j1]Sanjeev Rao Maddila, Dian Zhou:
Routing in general junctions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(11): 1174-1184 (1989)
Coauthor Index
aka: Shengguo Wang
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