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2020 – today
- 2023
[j27]Yongwoon Song
, Munhyung Lee, Hyukjun Lee:
High Bandwidth and Highly Available Packet Buffer Design Using Multi-Retention Time MRAM. IEEE Access 11: 98016-98024 (2023)- 2022
- [j26]Jeongbin Kim, Yongwoon Song, Kyungseon Cho, Hyukjun Lee, Hongil Yoon, Eui-Young Chung:
STT-MRAM-Based Multicontext FPGA for Multithreading Computing Environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1330-1343 (2022) - 2021
- [j25]Yongwoon Song, Jooyoung Hwang, Insoon Jo, Hyukjun Lee:
Highly Available Packet Buffer Design With Hybrid Nonvolatile Memory. IEEE Trans. Very Large Scale Integr. Syst. 29(11): 2008-2012 (2021) - 2020
- [j24]Minsik Oh, Kwangsu Kim, Duheon Choi, Hyukjun Lee, Eui-Young Chung:
Per-Operation Reusability Based Allocation and Migration Policy for Hybrid Cache. IEEE Trans. Computers 69(2): 158-171 (2020) - [j23]Tae-Hee You, Sangwoo Han, Young Min Park, Hyuk-Jun Lee, Eui-Young Chung:
Multitoken-Based Power Management for NAND Flash Storage Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2898-2910 (2020) - [c5]Chungseop Lee, Keonhyuk Lee, Mingoo Kang, Hyukjun Lee:
EANeM: Energy-Aware Network Stack Management for Mobile Devices. DAC 2020: 1-6
2010 – 2019
- 2019
- [j22]Bobae Kim, Hyukjun Lee:
IP-aware cache partition and replacement scheme for mobile computing devices. IEICE Electron. Express 16(15): 20190351 (2019) - [j21]Yongwoon Song, Dongkeon Choi, Hyuk-Jun Lee:
Designing a High Performance SRAM-DRAM Hybrid Memory Architecture for Packet Buffers. IEICE Trans. Electron. 102-C(12): 849-852 (2019) - [j20]Myeongjin Kim, Wontaeck Jung, Hyukjun Lee, Eui-Young Chung:
A Novel NAND Flash Memory Architecture for Maximally Exploiting Plane-Level Parallelism. IEEE Trans. Very Large Scale Integr. Syst. 27(8): 1957-1961 (2019) - 2018
- [j19]Chinam Kim, Hyukjun Lee:
A High-Bandwidth PCM-Based Memory System for Highly Available IP Routing Table Lookup. IEEE Comput. Archit. Lett. 17(2): 246-249 (2018) - [j18]Hyunwoo Park, Hyun So, Hyukjun Lee:
Application specific cache design using STT-RAM based block-RAM for FPGA-based soft processors. IEICE Electron. Express 15(10): 20180330 (2018) - [j17]Yoojin Kim, Yongwoon Song, Hyuk-Jun Lee:
Energy Efficient Mobile Positioning System Using Adaptive Particle Filter. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(6): 997-999 (2018) - [j16]Sungin Shin, Hyukjun Lee, Changhyeon Kim, Wonjin Sung, Jonghyun Park:
Parameterised codebook design based on channel statistics for efficient multi-rank MIMO transmission. IET Commun. 12(15): 1880-1890 (2018) - 2017
- [j15]Junghee Lee, Kalidas Ganesh, Hyuk-Jun Lee, Youngjae Kim:
FeSSD: A Fast Encrypted SSD Employing On-Chip Access-Control Memory. IEEE Comput. Archit. Lett. 16(2): 115-118 (2017) - [j14]Taehyun Kim, Jongbum Lim, Jinku Kim, Woo-Cheol Cho, Eui-Young Chung, Hyuk-Jun Lee:
Scalable Bandwidth Shaping Scheme via Adaptively Managed Parallel Heaps in Manycore-Based Network Processors. ACM Trans. Design Autom. Electr. Syst. 22(4): 59:1-59:26 (2017) - 2016
- [j13]Kwang-Ho Kim, Dae-Young Jung, Donghyun Lee, Hyuk-Jun Lee, Sung-Yong Park, Myoung-Wan Koo, Ji-Hwan Kim, Jeong-Sik Park, Hyung-Bae Jeon, Yun-Keun Lee:
Implementation of a large-scale language model adaptation in a cloud environment. Multim. Tools Appl. 75(9): 5029-5045 (2016) - 2014
- [j12]Kwonyong Lee, Yoonsung Nam, Taekhee Kim, Sungyong Park, Hyuk-Jun Lee, Jihoon Yang:
A dynamic block device reconfiguration algorithm in virtual MapReduce cluster. Clust. Comput. 17(4): 1171-1183 (2014) - [j11]Seunghak Yu, Sungroh Yoon, Eui-Young Chung, Hyuk-Jun Lee:
Design of a bitmap-based QoS-aware memory controller for a packet memory. IEICE Electron. Express 11(5): 20130983 (2014) - [j10]Jongbum Lim, Yongwoon Song, Hyuk-Jun Lee:
An optimal DRAM sizing and partitioning method for NVRAM based hybrid memory architecture. IEICE Electron. Express 11(19): 20140755 (2014) - [j9]Jongho Nang, Sangchul Kim, Hyuk-Jun Lee:
Classifying Useful Motion Vectors for Efficient Frame Rate Up Conversion of MC-DCT Encoded Video Streams. J. Inf. Sci. Eng. 30(6): 1755-1771 (2014) - [j8]Sang-Hoon Park, Dong-gun Kim, Kwanhu Bang, Hyuk-Jun Lee, Sungjoo Yoo, Eui-Young Chung:
An Adaptive Idle-Time Exploiting Method for Low Latency NAND Flash-Based Storage Devices. IEEE Trans. Computers 63(5): 1085-1096 (2014) - 2013
- [j7]Samkyu Won, Eui-Young Chung, DuckJu Kim, Junseop Chung, Bong-Seok Han, Hyuk-Jun Lee:
Page overwriting method for performance improvement of NAND flash memories. IEICE Electron. Express 10(6): 20130039 (2013) - [j6]Hyuk-Jun Lee, Seung-Chul Kim, Eui-Young Chung:
A Low-Power Packet Memory Architecture with a Latency-Aware Packet Mapping Method. IEICE Trans. Inf. Syst. 96-D(4): 963-966 (2013) - [j5]Sang Guun Yoo, Hyukjun Lee, Juho Kim:
A Performance and Usability Aware Secure Two-Factor User Authentication Scheme for Wireless Sensor Networks. Int. J. Distributed Sens. Networks 9 (2013) - [c4]Dae-Young Jung, Hyuk-Jun Lee, Sung-Yong Park, Myoung-Wan Koo, Ji-Hwan Kim, Jeong-Sik Park, Hyung-Bae Jeon, Yun-Keun Lee:
Implementation of a Large-Scale Language Model in a Cloud Environment for Human-Robot Interaction. ITCS 2013: 957-965 - 2012
- [j4]Hyuk-Jun Lee, Woo-Cheol Cho, Eui-Young Chung:
Analytical memory bandwidth model for many-core processor based systems. IEICE Electron. Express 9(18): 1461-1466 (2012)
2000 – 2009
- 2008
- [j3]Hyuk-Jun Lee, Eui-Young Chung:
Scalable QoS-Aware Memory Controller for High-Bandwidth Packet Memory. IEEE Trans. Very Large Scale Integr. Syst. 16(3): 289-301 (2008) - 2007
- [j2]Minje Jun, Kwanhu Bang, Hyuk-Jun Lee, Eui-Young Chung:
Latency-Aware Bus Arbitration for Real-Time Embedded Systems. IEICE Trans. Inf. Syst. 90-D(3): 676-679 (2007) - [j1]Eui-Young Chung, Hyuk-Jun Lee, Sung Woo Chung:
Scenario-Aware Bus Functional Modeling for Architecture-Level Performance Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(4): 875-878 (2007) - [c3]Minje Jun, Kwanhu Bang, Hyuk-Jun Lee, Naehyuck Chang, Eui-Young Chung:
Slack-based Bus Arbitration Scheme for Soft Real-time Constrained Embedded Systems. ASP-DAC 2007: 159-164 - 2000
- [c2]Hyuk-Jun Lee, Michael J. Flynn:
Coarse-grained carry architecture for FPGA (poster abstract). FPGA 2000: 217 - [c1]Hyuk-Jun Lee, Albert A. Liddicoat, Michael J. Flynn:
Exploiting Parallelism and Data Locality of Systolic Array Applications using Multi-Ported FPGA. PDPTA 2000
Coauthor Index
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