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ORCIDKazuyuki Tanimura
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Journal Articles
- 2024
[j4]Anton Okolnychyi, Chao Sun, Kazuyuki Tanimura, Russell Spitzer, Ryan Blue, Szehon Ho, Yufei Gu, Vishwanath Lakkundi, D. B. Tsai:
Petabyte-Scale Row-Level Operations in Data Lakehouses. Proc. VLDB Endow. 17(12): 4159-4172 (2024)- 2012
- [j3]Kazuyuki Tanimura, Nikil D. Dutt
:
HDRL: Homogeneous Dual-Rail Logic for DPA Attack Resistive Secure Circuit Design. IEEE Embed. Syst. Lett. 4(3): 57-60 (2012) - [j2]Giovanni Ansaloni, Kazuyuki Tanimura, Laura Pozzi, Nikil D. Dutt:
Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(12): 1803-1816 (2012) - 2009
- [j1]Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in GF(P) and GF(2n). IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(9): 2304-2317 (2009)
Conference and Workshop Papers
- 2012
- [c4]Kazuyuki Tanimura, Nikil D. Dutt:
LRCG: latch-based random clock-gating for preventing power analysis side-channel attacks. CODES+ISSS 2012: 453-462 - 2011
- [c3]Giovanni Ansaloni, Laura Pozzi, Kazuyuki Tanimura, Nikil D. Dutt:
Slack-aware scheduling on Coarse Grained Reconfigurable Arrays. DATE 2011: 1513-1516 - 2010
- [c2]Kazuyuki Tanimura, Nikil D. Dutt:
ExCCel: Exploration of Complementary Cells for Efficient DPA Attack Resistivity. HOST 2010: 52-55 - 2008
- [c1]Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2n). ASP-DAC 2008: 697-702
Coauthor Index
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