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Takeshi Nakayama
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2020 – today
- 2022
- [j8]Abudusaimi Abuduaini, Nobuyuki Shiraki, Naoki Honma, Takeshi Nakayama, Shoichi Iizuka:
Frequency Error Compensation of Unsynchronized Bistatic CW- MIMO Radar for Multiple Human-Body Localization. IEEE Trans. Biomed. Circuits Syst. 16(5): 882-890 (2022) - 2021
- [j7]Nobuyuki Shiraki, Naoki Honma, Kentaro Murata, Takeshi Nakayama, Shoichi Iizuka:
Estimation Method of the Number of Targets Using Cooperative Multi-Static MIMO Radar. IEICE Trans. Commun. 104-B(12): 1539-1546 (2021)
2010 – 2019
- 2019
- [j6]Dai Sasakawa, Naoki Honma, Takeshi Nakayama, Shoichi Iizuka:
Human Activity Identification by Height and Doppler RCS Information Detected by MIMO Radar. IEICE Trans. Commun. 102-B(7): 1270-1278 (2019) - [c8]Shoichi Iizuka, Takeshi Nakayama, Dai Sasakawa, Naoki Honma:
Non-restraint human authentication using MIMO array. IPIN (Short Papers/Work-in-Progress Papers) 2019: 408-415 - 2018
- [j5]Katsumi Sasaki, Naoki Honma, Takeshi Nakayama, Shoichi Iizuka:
RSSI-Based Living-Body Radar Using Single RF Front-End and Tunable Parasitic Antennas. IEICE Trans. Commun. 101-B(2): 392-399 (2018) - 2016
- [c7]Dai Sasakawa, Naoki Honma, Kentaro Nishimori, Takeshi Nakayama, Shoichi Iizuka:
Evaluation of fast human localization and tracking using MIMO radar in multi-path environment. PIMRC 2016: 1-6
2000 – 2009
- 2001
- [j4]Tatsuya Ishii, Kazuyoshi Oshima, Hiroshi Sato, Satoshi Noda, Jiro Kishimoto, Hiroaki Kotani, Atsushi Nozoe, Kazunori Furusawa, Takayuki Yoshitake, Masataka Kato, Masahito Takahashi, Akihiko Sato, Shoji Kubono, Kiichi Manita, Kenji Koda, Takeshi Nakayama, Akira Hosogane:
A 126.6-mm2 AND-type 512-Mb flash memory with 1.8-V power supply. IEEE J. Solid State Circuits 36(11): 1707-1712 (2001)
1990 – 1999
- 1999
- [j3]Atsushi Nozoe, Hiroaki Kotani, Tetsuya Tsujikawa, Keiichi Yoshida, Kazunori Furusawa, Masataka Kato, Toshiaki Nishimoto, Hitoshi Kume, Hideaki Kurata, Naoki Miyamoto, Shoji Kubono, Michitaro Kanamitsu, Kenji Koda, Takeshi Nakayama, Yasuhiro Kouro, Akira Hosogane, Natsuo Ajika, Kiyoteru Kobayashi:
A 256-Mb multilevel flash memory with 2-MB/s program rate for mass storage applications. IEEE J. Solid State Circuits 34(11): 1544-1550 (1999) - 1998
- [c6]Jien Kato, Toyohide Watanabe, Takeshi Nakayama, Lishing Guo, Hitoshi Kato:
A model-based approach for recognizing folding process of origami. ICPR 1998: 1808-1811 - 1997
- [c5]Jien Kato, Toyohide Watanabe, Takeshi Nakayama:
Recognition of Essential Folding Operations: A Step for Interpreting Illustrated Books of Origami. ICDAR 1997: 81-85 - [c4]Hiroyuki Yamamoto, Takeshi Nakayama, Hiroshi Ninomiya, Hideki Asai:
Application of neuro-based optimization algorithm to three dimensional cylindric puzzles. ICNN 1997: 1246-1250 - 1996
- [c3]Hideki Asai, Takeshi Nakayama, Hiroshi Ninomiya:
Tiling algorithm with fitting violation function for analog neural array. ICNN 1996: 565-570 - [c2]Qin Luo, Takahiro Watanabe, Takeshi Nakayama:
Identifying contents page of documents. ICPR 1996: 696-700 - 1995
- [c1]Hiroshi Ninomiya, Kazumichi Sato, Takeshi Nakayama, Hideki Asai:
Neural network approach to traveling salesman problem based on hierarchical city adjacency. ICNN 1995: 2626-2631 - 1994
- [j2]Shin'ichi Kobayashi, Hiroaki Nakai, Yuichi Kunori, Takeshi Nakayama, Yoshikazu Miyawaki, Yasushi Terada, Hiroshi Onoda, Natsuo Ajika, Masahiro Hatanaka, Hirokazu Miyoshi, Tsutomu Yoshihara:
Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory. IEEE J. Solid State Circuits 29(4): 454-460 (1994)
1980 – 1989
- 1988
- [j1]Yasushi Terada, Kazuo Kobayashi, Takeshi Nakayama, Hideaki Arima, Tsutomu Yoshihara:
A new architecture for the NVRAM-an EEPROM backed-up dynamic RAM. IEEE J. Solid State Circuits 23(1): 86-90 (1988)
Coauthor Index
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