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Veerapaneni Nagbhushan

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2000 – 2009

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2008
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Veerapaneni Nagbhushan, C. Y. Roger Chen:
Modeling and reduction of complex timing constraints in high performance digital circuits. ICCD 2008: 544-550
2007
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Veerapaneni Nagbhushan, C. Y. Roger Chen:
Algorithms to simplify multi-clock/edge timing constraints. ICCD 2007: 444-449

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