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Jaemin Jang
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2020 – today
- 2024
- [c4]Jinhyung Lee, Kyungjun Cho, Chang Kwon Lee, Yeonho Lee, Jae-Hyung Park, Su-Hyun Oh, Yucheon Ju, Chunseok Jeong, Ho Sung Cho, Jaeseung Lee, Tae-Sik Yun, Jin Hee Cho, Sangmuk Oh, Junil Moon, Young-Jun Park, Hong-Seok Choi, In-Keun Kim, Seung Min Yang, Sun-Yeol Kim, Jaemin Jang, Jinwook Kim, Seong-Hee Lee, Younghyun Jeon, Juhyung Park, Tae-Kyun Kim, Dongyoon Ka, Sanghoon Oh, Jinse Kim, Junyeol Jeon, Seonhong Kim, Kyeong Tae Kim, Taeho Kim, Hyeonjin Yang, Dongju Yang, Minseop Lee, Heewoong Song, Dongwook Jang, Junghyun Shin, Hyunsik Kim, Chang-Ki Baek, Hajun Jeong, Jongchan Yoon, Seung-Kyun Lim, Kyo Yun Lee, Young Jun Koo, Myeong-Jae Park, Joohwan Cho, Jonghwan Kim:
13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization. ISSCC 2024: 238-240
2010 – 2019
- 2019
- [j11]Jaemin Jang, Wongyu Shin, Jungwhan Choi, Yongju Kim, Lee-Sup Kim:
Sparse-Insertion Write Cache to Mitigate Write Disturbance Errors in Phase Change Memory. IEEE Trans. Computers 68(5): 752-764 (2019) - [j10]Jungwhan Choi, Jaemin Jang, Lee-Sup Kim:
DC-PCM: Mitigating PCM Write Disturbance with Low Performance Overhead by Using Detection Cells. IEEE Trans. Computers 68(12): 1741-1754 (2019) - 2018
- [j9]Hoseok Seol, Wongyu Shin, Jaemin Jang, Jungwhan Choi, Hakseung Lee, Lee-Sup Kim:
Elaborate Refresh: A Fine Granularity Retention Management for Deep Submicron DRAMs. IEEE Trans. Computers 67(10): 1403-1415 (2018) - 2017
- [j8]Jaemin Jang, Taemin Ahn, Junghee Han:
A new application-layer overlay platform for better connected vehicles. Int. J. Distributed Sens. Networks 13(11) (2017) - [j7]Jaemin Jang, Wongyu Shin, Jungwhan Choi, Jinwoong Suh, Yongkee Kwon, Yongju Kim, Lee-Sup Kim:
Refresh-Aware Write Recovery Memory Controller. IEEE Trans. Computers 66(4): 688-701 (2017) - [j6]Wongyu Shin, Jaemin Jang, Jungwhan Choi, Jinwoong Suh, Yongkee Kwon, Youngsuk Moon, Lee-Sup Kim:
Rank-Level Parallelism in DRAM. IEEE Trans. Computers 66(7): 1274-1280 (2017) - [j5]Wongyu Shin, Jaemin Jang, Jungwhan Choi, Jinwoong Suh, Lee-Sup Kim:
Bank-Group Level Parallelism. IEEE Trans. Computers 66(8): 1428-1434 (2017) - [j4]Hoseok Seol, Wongyu Shin, Jaemin Jang, Jungwhan Choi, Jinwoong Suh, Lee-Sup Kim:
In-DRAM Data Initialization. IEEE Trans. Very Large Scale Integr. Syst. 25(11): 3251-3254 (2017) - 2016
- [j3]Wongyu Shin, Jungwhan Choi, Jaemin Jang, Jinwoong Suh, Yongkee Kwon, Youngsuk Moon, Hongsik Kim, Lee-Sup Kim:
Q-DRAM: Quick-Access DRAM with Decoupled Restoring from Row-Activation. IEEE Trans. Computers 65(7): 2213-2227 (2016) - [j2]Wongyu Shin, Jungwhan Choi, Jaemin Jang, Jinwoong Suh, Youngsuk Moon, Yongkee Kwon, Lee-Sup Kim:
DRAM-Latency Optimization Inspired by Relationship between Row-Access Time and Refresh Timing. IEEE Trans. Computers 65(10): 3027-3040 (2016) - [j1]Ji-Hoon Lim, Jun-Hyun Bae, Jaemin Jang, Hae-Kang Jung, Hyunbae Lee, Yongju Kim, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMs. IEEE Trans. Circuits Syst. II Express Briefs 63-II(2): 141-145 (2016) - [c3]Hoseok Seol, Wongyu Shin, Jaemin Jang, Jungwhan Choi, Jinwoong Suh, Lee-Sup Kim:
Energy Efficient Data Encoding in DRAM Channels Exploiting Data Value Similarity. ISCA 2016: 719-730 - 2015
- [c2]Jungwhan Choi, Wongyu Shin, Jaemin Jang, Jinwoong Suh, Yongkee Kwon, Youngsuk Moon, Lee-Sup Kim:
Multiple clone row DRAM: a low latency and area optimized DRAM. ISCA 2015: 223-234 - 2012
- [c1]Kibong Koo, Sunghwa Ok, Yonggu Kang, Seungbong Kim, Choungki Song, Hyeyoung Lee, Hyungsoo Kim, Yongmi Kim, Jeonghun Lee, Seunghan Oak, Yosep Lee, Jungyu Lee, Joongho Lee, Hyungyu Lee, Jaemin Jang, Jongho Jung, Byeongchan Choi, Yong-Ju Kim, Youngdo Hur, Yunsaing Kim, Byong-Tae Chung, Yongtak Kim:
A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture. ISSCC 2012: 40-41
Coauthor Index
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