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2020 – today
- 2023
[j54]Daijoon Hyun
, Younggwang Jung, Youngsoo Shin:
Airgap Insertion and Layer Reassignment Under Setup and Hold Timing Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(3): 987-999 (2023)- [c98]Daijoon Hyun, Younggwang Jung, Insu Cho, Youngsoo Shin:
Decoupling Capacitor Insertion Minimizing IR-Drop Violations and Routing DRVs. ASP-DAC 2023: 271-276 - 2022
- [c97]Youngsoo Shin:
Supporting Users' Decision-Making Experiences through Hyper-Personalized Human-Technology Interactions. onference on Designing Interactive Systems (Companion Volume) 2022: 8-11 - [c96]Yonghwi Kwon, Youngsoo Shin:
Fast Prediction of Dynamic IR-Drop Using Recurrent U-Net Architecture. MLCAD 2022: 71-76 - 2021
- [j53]Youngsoo Shin:
Computational Lithography Using Machine Learning Models. IPSJ Trans. Syst. LSI Des. Methodol. 14: 2-10 (2021) - [c95]Youngsoo Shin, Ruth Barankevich, Jina Lee, Saleh Kalantari:
PENCODER: Design for Prospective Memory and Older Adults. CHI Extended Abstracts 2021: 371:1-371:7 - [c94]Sunwha Koh, Younggwang Jung, Daijoon Hyun, Youngsoo Shin:
Routability Optimization for Extreme Aspect Ratio Design Using Convolutional Neural Network. ISCAS 2021: 1-4 - [c93]Yonghwi Kwon, Giyoon Jung, Daijoon Hyun, Youngsoo Shin:
Dynamic IR Drop Prediction Using Image-to-Image Translation Neural Network. ISCAS 2021: 1-5 - [c92]Youngsoo Shin, Jungkyoon Yoon:
Towards Designing Human-Centered Time Management Interfaces: The Development of 14 UX Design Guidelines for Time-related Experiences in Mobile HCI. MobileHCI (Extended Abstracts) 2021: 15:1-15:7 - 2020
- [c91]Younggwang Jung, Daijoon Hyun, Youngsoo Shin:
Integrated Airgap Insertion and Layer Reassignment for Circuit Timing optimization. ASP-DAC 2020: 32-37 - [c90]Wonjae Lee, Yonghwi Kwon, Youngsoo Shin:
Fast ECO Leakage Optimization Using Graph Convolutional Network. ACM Great Lakes Symposium on VLSI 2020: 187-192 - [c89]Sunwha Koh, Yonghwi Kwon, Youngsoo Shin:
Pre-layout clock tree estimation and optimization using artificial neural network. ISLPED 2020: 193-198
2010 – 2019
- 2019
- [j52]Daijoon Hyun, Younggwang Jung, Youngsoo Shin:
Selective Use of Stitch-Induced Via for V0 Mask Reduction: Standard Cell Design and Placement Optimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(12): 1711-1719 (2019) - [j51]Suhyeong Choi, Seongbo Shim, Youngsoo Shin:
Neural Network Classifier-Based OPC With Imbalanced Training Data. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(5): 938-948 (2019) - [j50]Jinwook Jung, Gi-Joon Nam, Woohyun Chung, Youngsoo Shin:
Integrated Latch Placement and Cloning for Timing Optimization. ACM Trans. Design Autom. Electr. Syst. 24(2): 22:1-22:17 (2019) - [j49]Daijoon Hyun, Youngsoo Shin:
Integrated Approach of Airgap Insertion for Circuit Timing Optimization. ACM Trans. Design Autom. Electr. Syst. 24(2): 24:1-24:22 (2019) - [j48]Youngsoo Song, Daijoon Hyun, Jingon Lee, Jinwook Jung, Youngsoo Shin:
Cut Optimization for Redundant Via Insertion in Self-Aligned Double Patterning. ACM Trans. Design Autom. Electr. Syst. 24(6): 61:1-61:21 (2019) - [c88]Daijoon Hyun, Yuepeng Fan, Youngsoo Shin:
Accurate Wirelength Prediction for Placement-Aware Synthesis through Machine Learning. DATE 2019: 324-327 - [c87]Yonghwi Kwon, Inhak Han, Youngsoo Shin:
Clock Gating Synthesis of Netlist with Cyclic Logic Paths. ICCAD 2019: 1-6 - [c86]Cheongwon Lee, Youngsoo Song, Youngsoo Shin:
Endurance Enhancement of Multi-Level Cell Phase Change Memory. ICCAD 2019: 1-8 - [c85]Youngsoo Song, Jinwook Jung, Youngsoo Shin:
Standard Cell Layout Design and Placement Optimization for TFET-Based Circuits. ISCAS 2019: 1-5 - 2018
- [j47]Youngsoo Shin, Jinwoo Kim:
Data-centered persuasion: Nudging user's prosocial behavior and designing social innovation. Comput. Hum. Behav. 80: 168-178 (2018) - [j46]Youngsoo Shin:
Recap of the 23rd Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE Des. Test 35(3): 100-101 (2018) - [j45]Sangmin Kim, Youngsoo Shin:
Module grouping to reduce the area of test wrappers in SoCs. Integr. 60: 39-47 (2018) - [j44]Yeongmin Lee, Min-Gyu Park, Youngbae Hwang, Youngsoo Shin, Chong-Min Kyung:
Memory-Efficient Parametric Semiglobal Matching. IEEE Signal Process. Lett. 25(2): 194-198 (2018) - [j43]Jinwook Jung, Gi-Joon Nam, Lakshmi N. Reddy, Iris Hui-Ru Jiang, Youngsoo Shin:
OWARU: Free Space-Aware Timing-Driven Incremental Placement With Critical Path Smoothing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(9): 1825-1838 (2018) - [j42]Suhyeong Choi, Seongbo Shim, Youngsoo Shin:
Electrothermal Analysis With Nonconvective Boundary Conditions. IEEE Trans. Circuits Syst. II Express Briefs 65-II(8): 1044-1048 (2018) - [j41]Inhak Han, Youngsoo Shin:
Folded Circuit Synthesis: Min-Area Logic Synthesis Using Dual-Edge-Triggered Flip-Flops. ACM Trans. Design Autom. Electr. Syst. 23(5): 61:1-61:21 (2018) - [c84]Daijoon Hyun, Youngsoo Shin:
Automatic insertion of airgap with design rule constraints. ASP-DAC 2018: 381-386 - [c83]Kiwon Yoon, Daijoon Hyun, Youngsoo Shin:
Fast Timing Analysis of Non-Tree Clock Network with Shorted Wires. ACM Great Lakes Symposium on VLSI 2018: 279-284 - [c82]Daijoon Hyun, Jaewoo Seo, Youngsoo Shin:
Library Optimization for Near-Threshold Voltage Design. ISCAS 2018: 1-4 - [c81]Yonghwi Kwon, Jinwook Jung, Inhak Han, Youngsoo Shin:
Transient Clock Power Estimation of Pre-CTS Netlist. ISCAS 2018: 1-4 - [c80]Jingon Lee, Jinwook Jung, Youngsoo Shin:
Fast Timing Analysis of Transistor-Level Full Custom Digital Circuits. ISCAS 2018: 1-4 - [c79]Joonhyuk Cho, Gangmin Cho, Youngsoo Shin:
Optimization of Machine Learning Guided Optical Proximity Correction. MWSCAS 2018: 921-924 - [e2]Youngsoo Shin:
23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018, Jeju, Korea (South), January 22-25, 2018. IEEE 2018, ISBN 978-1-5090-0602-1 [contents] - 2017
- [j40]Youngsoo Shin, Chaerin Im, Hyosun Oh, Jinwoo Kim:
Design for experience innovation: understanding user experience in new product development. Behav. Inf. Technol. 36(12): 1218-1234 (2017) - [j39]Seongbo Shim, Youngsoo Shin:
Fast Verification of Guide-Patterns for Directed Self-Assembly Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(9): 1522-1531 (2017) - [j38]Seongbo Shim, Woohyun Chung, Youngsoo Shin:
Lithography Defect Probability and Its Application to Physical Design Optimization. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 271-285 (2017) - [c78]Jaewoo Seo, Jinwook Jung, Sangmin Kim, Youngsoo Shin:
Pin Accessibility-Driven Cell Layout Redesign and Placement Optimization. DAC 2017: 54:1-54:6 - [c77]Wachirawit Ponghiran, Seongbo Shim, Youngsoo Shin:
Cut mask optimization for multi-patterning directed self-assembly lithography. DATE 2017: 1498-1503 - [c76]Youngsoo Song, Sangmin Kim, Youngsoo Shin:
Timing-aware wire width optimization for SADP process. DATE 2017: 1639-1642 - [c75]Youngsoo Song, Jinwook Jung, Youngsoo Shin:
Redundant Via Insertion with Cut Optimization for Self-Aligned Double Patterning. ACM Great Lakes Symposium on VLSI 2017: 137-142 - [c74]Daijoon Hyun, Wachirawit Ponghiran, Youngsoo Shin:
Clock tree optimization through selective airgap insertion. ISQED 2017: 203-208 - [c73]Youngsoo Song, Jinwook Jung, Youngsoo Shin:
Redundant Via insertion in SADP process with cut merging and optimization. VLSI-SoC 2017: 1-6 - 2016
- [j37]Sangmin Kim, Seungwhun Paik, Seokhyeong Kang, Youngsoo Shin:
Wakeup scheduling and its buffered tree synthesis for power gating circuits. Integr. 53: 157-170 (2016) - [j36]Sangmin Kim, Seokhyeong Kang, Youngsoo Shin:
Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree Optimization. ACM Trans. Design Autom. Electr. Syst. 21(3): 51:1-51:23 (2016) - [j35]Insup Shin, Jae-Joon Kim, Yu-Shiang Lin, Youngsoo Shin:
One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 600-612 (2016) - [c72]Seongbo Shim, Suhyeong Choi, Youngsoo Shin:
Machine learning (ML)-based lithography optimizations. APCCAS 2016: 530-533 - [c71]Seongbo Shim, Youngsoo Shin:
Mask optimization for directed self-assembly lithography: Inverse DSA and inverse lithography. ASP-DAC 2016: 83-88 - [c70]Inhak Han, Daijoon Hyun, Youngsoo Shin:
Buffer insertion to remove hold violations at multiple process corners. ASP-DAC 2016: 232-237 - [c69]Jinwook Jung, Youngsoo Shin:
Localized DNA circuit design with majority gates. BioCAS 2016: 172-175 - [c68]Seongbo Shim, Woohyun Chung, Youngsoo Shin:
Redundant via insertion for multiple-patterning directed-self-assembly lithography. DAC 2016: 41:1-41:6 - [c67]Woohyun Chung, Seongbo Shim, Youngsoo Shin:
Redundant via insertion in directed self-assembly lithography. DATE 2016: 55-60 - [c66]Jinwook Jung, Gi-Joon Nam, Lakshmi N. Reddy, Iris Hui-Ru Jiang, Youngsoo Shin:
OWARU: free space-aware timing-driven incremental placement. ICCAD 2016: 8 - [c65]Inhak Han, Jonggyu Kim, Joonhwan Yi, Youngsoo Shin:
Register grouping for synthesis of clock gating logic. ICICDT 2016: 1-4 - [c64]Seongbo Shim, Woohyun Chung, Youngsoo Shin:
Placement optimization for MP-DSAL compliant layout. ICICDT 2016: 1-4 - [c63]Kiwon Yoon, Seongbo Shim, Youngsoo Shin:
Crosslink insertion for minimizing OCV clock skew. ISCAS 2016: 2587-2590 - [c62]Kiwon Yoon, Suhyeong Choi, Youngsoo Shin:
Area efficient neuromorphic circuit based on stochastic computation. ISOCC 2016: 73-74 - [e1]Youngsoo Shin, Chi-Ying Tsui, Jae-Joon Kim, Kiyoung Choi, Ricardo Reis:
VLSI-SoC: Design for Reliability, Security, and Low Power - 23rd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected Papers. IFIP Advances in Information and Communication Technology 483, Springer 2016, ISBN 978-3-319-46096-3 [contents] - 2015
- [j34]Youngsoo Shin, Bumho Lee, Jinwoo Kim:
Prosocial Activists in SNS: The Impact of Isomorphism and Social Presence on Prosocial Behaviors. Int. J. Hum. Comput. Interact. 31(12): 939-958 (2015) - [j33]Insup Shin, Jae-Joon Kim, Youngsoo Shin:
Aggressive Voltage Scaling Through Fast Correction of Multiple Errors With Seamless Pipeline Operation. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(2): 468-477 (2015) - [j32]Seongbo Shim, Jae Wook Lee, Youngsoo Shin:
An Analytical Approach to Thermal Design and Optimization With a Temperature-Dependent Power Model. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(3): 816-824 (2015) - [c61]Woohyun Chung, Seongbo Shim, Youngsoo Shin:
Identifying redundant inter-cell margins and its application to reducing routing congestion. DATE 2015: 1659-1664 - [c60]Seongbo Shim, Woohyun Chung, Youngsoo Shin:
Defect Probability of Directed Self-Assembly Lithography: Fast Identification and Post-Placement Optimization. ICCAD 2015: 404-409 - [c59]Jinwook Jung, Daijoon Hyun, Youngsoo Shin:
Physical synthesis of DNA circuits with spatially localized gates. ICCD 2015: 259-265 - [c58]Seongbo Shim, Youngsoo Shin:
Physical design and mask optimization for directed self-assembly lithography (DSAL). VLSI-SoC 2015: 80-85 - [c57]Youngsoo Shin, Chi-Ying Tsui:
Message from the technical program chairs. VLSI-SoC 2015: IX - 2014
- [j31]Youngsoo Shin, Insup Shin, Donkyu Baek, Duckhwan Kim, Seungwhun Paik:
HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask Patterning. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(1): 146-159 (2014) - [j30]Inhak Han, Youngsoo Shin:
Simplifying Clock Gating Logic by Matching Factored Forms. IEEE Trans. Very Large Scale Integr. Syst. 22(6): 1338-1349 (2014) - [c56]Seongbo Shim, Yoojong Lee, Youngsoo Shin:
Lithographic defect aware placement using compact standard Cells without inter-cell margin. ASP-DAC 2014: 47-52 - [c55]Insup Shin, Jae-Joon Kim, Youngsoo Shin:
Power minimization of pipeline architecture through 1-cycle error correction and voltage scaling. ASP-DAC 2014: 179-184 - [c54]Jinwook Jung, Dongsoo Lee, Youngsoo Shin:
Design and Optimization of Multiple-Mesh Clock Network. VLSI-SoC (Selected Papers) 2014: 39-57 - 2013
- [j29]Donkyu Baek, Insup Shin, Youngsoo Shin:
Accurate gate delay Extraction for Timing Analysis of Body-Biased Circuits. J. Circuits Syst. Comput. 22(8) (2013) - [c53]Sangmin Kim, Duckhwan Kim, Youngsoo Shin:
Pulsed-latch ASIC synthesis in industrial design flow. ASP-DAC 2013: 356-361 - [c52]Seongbo Shim, Minyoung Mo, Sangmin Kim, Youngsoo Shin:
Analysis and minimization of short-circuit current in mesh clock network. ICCD 2013: 459-462 - [c51]Inhak Han, Youngsoo Shin:
Folded circuit synthesis: Logic simplification using dual edge-triggered flip-flops. ICICDT 2013: 17-20 - [c50]Insup Shin, Jae-Joon Kim, Yu-Shiang Lin, Youngsoo Shin:
A pipeline architecture with 1-cycle timing error correction for low voltage operations. ISLPED 2013: 199-204 - 2012
- [j28]Jun Seomun, Insup Shin, Youngsoo Shin:
Synthesis of Active-Mode Power-Gating Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(3): 391-403 (2012) - [j27]Seungwhun Paik, Inhak Han, Sangmin Kim, Youngsoo Shin:
Clock Gating Synthesis of Pulsed-Latch Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(7): 1019-1030 (2012) - [j26]Insup Shin, Seungwhun Paik, Dongwan Shin, Youngsoo Shin:
HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures. IEEE Trans. Very Large Scale Integr. Syst. 20(4): 593-604 (2012) - [j25]Nam Sung Kim, Abhishek A. Sinkar, Jun Seomun, Youngsoo Shin:
Maximizing Frequency and Yield of Power-Constrained Designs Using Programmable Power-Gating. IEEE Trans. Very Large Scale Integr. Syst. 20(10): 1885-1890 (2012) - [c49]Insup Shin, Donkyu Baek, Youngsoo Shin:
Introducing irregularity to routing architecture of structured ASIC for better routability. FPT 2012: 224-228 - [c48]Donkyu Baek, Insup Shin, Youngsoo Shin:
Gate delay modeling for static timing analysis of body-biased circuits. ICICDT 2012: 1-4 - [c47]Inhak Han, Youngsoo Shin:
Synthesis of clock gating logic through factored form matching. ICICDT 2012: 1-4 - 2011
- [j24]Youngsoo Shin, Seungwhun Paik:
Pulsed-Latch Circuits: A New Dimension in ASIC Design. IEEE Des. Test Comput. 28(6): 50-57 (2011) - [j23]Lee-eun Yu, Changsik Shin, Seungwhun Paik, Jing-Jia Liou, Youngsoo Shin:
Sampling Correlation Sources for Timing Yield Analysis of Sequential Circuits with Clock Networks. J. Circuits Syst. Comput. 20(8): 1547-1569 (2011) - [j22]Seungwhun Paik, Seonggwan Lee, Youngsoo Shin:
Retiming Pulsed-Latch Circuits With Regulating Pulse Width. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(8): 1114-1127 (2011) - [j21]Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang:
Pulsed-Latch Aware Placement for Timing-Integrity Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(12): 1856-1869 (2011) - [j20]Jun Seomun, Youngsoo Shin:
Design and Optimization of Power-Gated Circuits With Autonomous Data Retention. IEEE Trans. Very Large Scale Integr. Syst. 19(2): 227-236 (2011) - [c46]Sangmin Kim, Inhak Han, Seungwhun Paik, Youngsoo Shin:
Pulser gating: A clock gating of pulsed-latch circuits. ASP-DAC 2011: 190-195 - [c45]Donkyu Baek, Insup Shin, Seungwhun Paik, Youngsoo Shin:
Selectively patterned masks: Structured ASIC with asymptotically ASIC performance. ASP-DAC 2011: 376-381 - [c44]Jaeha Kung, Inhak Han, Sachin S. Sapatnekar, Youngsoo Shin:
Thermal signature: a simple yet accurate thermal index for floorplan optimization. DAC 2011: 108-113 - [c43]Seungwhun Paik, Gi-Joon Nam, Youngsoo Shin:
Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power. ICCAD 2011: 640-646 - [c42]Jaeha Kung, Youngsoo Shin:
Compact thermal models: Assessment and pitfalls. ISOCC 2011: 337-340 - 2010
- [j19]Byunghee Choi, Youngsoo Shin:
Lookup Table-Based Adaptive Body biasing of Multiple Macros for Process Variation Compensation and Low Leakage. J. Circuits Syst. Comput. 19(7): 1449-1464 (2010) - [j18]Hyein Lee, Seungwhun Paik, Youngsoo Shin:
Pulse Width Allocation and Clock Skew Scheduling: Optimizing Sequential Circuits Based on Pulsed Latches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(3): 355-366 (2010) - [j17]Seungwhun Paik, Insup Shin, Taewhan Kim, Youngsoo Shin:
HLS-l: A High-Level Synthesis Framework for Latch-Based Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 657-670 (2010) - [j16]Youngsoo Shin, Jun Seomun, Kyu-Myung Choi, Takayasu Sakurai:
Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs. ACM Trans. Design Autom. Electr. Syst. 15(4): 28:1-28:37 (2010) - [j15]Hyung-Ock Kim, Bong Hyun Lee, Jong-Tae Kim, Jung Yun Choi, Kyu-Myung Choi, Youngsoo Shin:
Supply Switching With Ground Collapse for Low-Leakage Register Files in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 18(3): 505-509 (2010) - [c41]Jun Seomun, Seungwhun Paik, Youngsoo Shin:
Bounded potential slack: enabling time budgeting for dual-Vt allocation of hierarchical design. ASP-DAC 2010: 581-586 - [c40]Seungwhun Paik, Lee-eun Yu, Youngsoo Shin:
Statistical time borrowing for pulsed-latch circuit designs. ASP-DAC 2010: 675-680 - [c39]Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang:
Pulsed-latch aware placement for timing-integrity optimization. DAC 2010: 280-285 - [c38]Jun Seomun, Insup Shin, Youngsoo Shin:
Synthesis and implementation of active mode power gating circuits. DAC 2010: 487-492 - [c37]Seungwhun Paik, Sangmin Kim, Youngsoo Shin:
Wakeup synthesis and its buffered tree construction for power gating circuit designs. ISLPED 2010: 413-418
2000 – 2009
- 2009
- [j14]Youngsoo Shin, Seungwhun Paik, Hyung-Ock Kim:
Semicustom Design of Zigzag Power-Gated Circuits in Standard Cell Elements. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(3): 327-339 (2009) - [j13]Eunjoo Choi, Changsik Shin, Youngsoo Shin:
ssr HLShbox-ssr pg: High-Level Synthesis of Power-Gated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(3): 451-456 (2009) - [j12]Jaehyun Kim, Chungki Oh, Youngsoo Shin:
Minimizing leakage power of sequential circuits through mixed-Vt flip-flops and multi-Vt combinational gates. ACM Trans. Design Autom. Electr. Syst. 15(1): 4:1-4:22 (2009) - [c36]Insup Shin, Seungwhun Paik, Youngsoo Shin:
Register allocation for high-level synthesis using dual supply voltages. DAC 2009: 937-942 - [c35]Seungwhun Paik, Insup Shin, Youngsoo Shin:
HLS-l: High-level synthesis of high performance latch-based circuits. DATE 2009: 1112-1117 - [c34]Seonggwan Lee, Seungwhun Paik, Youngsoo Shin:
Retiming and time borrowing: Optimizing high-performance pulsed-latch-based circuits. ICCAD 2009: 375-380 - [c33]Nam Sung Kim, Jun Seomun, Abhishek A. Sinkar, Jungseob Lee, Tae Hee Han, Ken Choi, Youngsoo Shin:
Frequency and yield optimization using power gates in power-constrained designs. ISLPED 2009: 121-126 - 2008
- [j11]Jun Seomun, Jae-Hyun Kim, Youngsoo Shin:
Skewed Flip-Flop and Mixed-Vt Gates for Minimizing Leakage in Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11): 1956-1968 (2008) - [c32]Jinseob Jeong, Seungwhun Paik, Youngsoo Shin:
Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation. ASP-DAC 2008: 629-634 - [c31]Seungwhun Paik, Youngsoo Shin:
Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements. DAC 2008: 600-605 - [c30]Hyein Lee, Seungwhun Paik, Youngsoo Shin:
Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits. ICCAD 2008: 224-229 - [c29]Eunjoo Choi, Youngsoo Shin:
3-D thermal simulation with dynamic power profiles. ISCAS 2008: 2765-2768 - [c28]Eunjoo Choi, Changsik Shin, Taewhan Kim, Youngsoo Shin:
Power-gating-aware high-level synthesis. ISLPED 2008: 39-44 - 2007
- [j10]