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ORCIDToshinari Takayanagi
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2000 – 2009
- 2007
[c3]Vincent von Kaenel, Toshinari Takayanagi:
Dual True Random Number Generators for Cryptographic Applications Embedded on a 200 Million Device Dual CPU SoC. CICC 2007: 269-272- [c2]Zongjian Chen, Priya Ananthanarayanan, Sukalp Biswas, Brian Campbell, Hao Chen, Shaishav Desai, Dominic Go, Rajat Goel, Vincent von Kaenel, Jason Kassoff, Fabian Klass, Weichun Ku, Tony Li, Jonathon Lin, Khurram Malik, Anup Mehta, Daniel Murray, Eric Shiu, Chris Shuler, Sribalan Santhanam, Greg Scott, Junji Sugisawa, Toshinari Takayanagi, Honkai John Tarn, Pradeep Trivedi, James Wang, Ricky Wen, John Yong:
A 25W SoC with Dual 2GHz Power Cores and Integrated Memory and I/O Subsystems. ISSCC 2007: 104-105 - 2005
- [j3]Toshinari Takayanagi, Jinuk Luke Shin, Bruce Petrick, Jeffrey Y. Su, Howard Levy, Ha Pham, Jinseung Son, Nathan Moon, Dina Bistry, Umesh Nair, Mandeep Singh, Vikas Mathur, Ana Sonia Leon:
A dual-core 64-bit ultraSPARC microprocessor for dense server applications. IEEE J. Solid State Circuits 40(1): 7-18 (2005) - 2004
- [c1]Toshinari Takayanagi, Jinuk Luke Shin, Bruce Petrick, Jeffrey Y. Su, Ana Sonia Leon:
A dual-core 64b ultraSPARC microprocessor for dense server applications. DAC 2004: 673-677 - 2001
- [j2]Ken-ichi Agawa, Hiroyuki Hara, Toshinari Takayanagi, Tadahiro Kuroda:
A bitline leakage compensation scheme for low-voltage SRAMs. IEEE J. Solid State Circuits 36(5): 726-734 (2001) - 2000
- [j1]Masafumi Takahashi, Tsuyoshi Nishikawa, Mototsugu Hamada, Toshinari Takayanagi, Hideho Arakida, Noriaki Machida, Hideaki Yamamoto, Toshihide Fujiyoshi, Yoko Ohashi, Osamu Yamagishi, Tatsuo Samata, Atsushi Asano, Toshihiro Terazawa, Kenji Ohmori, Yoshinori Watanabe, Hiroki Nakamura, Shigenobu Minami, Tadahiro Kuroda, Tohru Furuyama:
A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM. IEEE J. Solid State Circuits 35(11): 1713-1721 (2000)
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