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ORCIDQiang Yang 0006
Person information
- affiliation: University of Amsterdam, The Netherlands
Other persons with the same name
- Qiang Yang — disambiguation page
- Qiang Yang 0001 — Hong Kong University of Science and Technology, Department of Computer Science, Kowloon, Hong Kong (and 2 more)
- Qiang Yang 0002 — Shandong University of Science and Technology, China
- Qiang Yang 0003
![[0000-0002-6570-1516]](https://dblp.dagstuhl.de/img/orcid-mark.12x12.png "0000-0002-6570-1516")
— Harbin Institute of Technology, China - Qiang Yang 0004 — Zhejiang University, College of Electrical Engineering, Hangzhou, China (and 4 more)
- Qiang Yang 0005 — Jilin University, Changchun Jilin, China
- Qiang Yang 0007 — Yangtze University, College of Computer Science, JingZhou, China
- Qiang Yang 0008 — Nanjing University of Information Science and Technology, School of Artificial Intelligence, China (and 2 more)
- Qiang Yang 0009 — Tsinghua University, State Key Laboratory of Hydroscience and Hydraulic Engineering, Beijing, China
- Qiang Yang 0010 — Sun Yat-sen University, School of Information Science and Technology, China
- Qiang Yang 0011 — University of Manchester, UK
- Qiang Yang 0012 — Chinese Academy of Sciences, Institute of Computing Technology, State Key Laboratory of Computer Architecture, China
- Qiang Yang 0013 — Huazhong University of Science and Technology (HUST), Wuhan, China
- Qiang Yang 0014 — Northeastern University, Shenyang, China
- Qiang Yang 0015 — University of Florida, Department of Health Outcomes and Biomedical Informatics, Gainesville, FL, USA (and 2 more)
- Qiang Yang 0016 — Sichuan University, College of Electronics and Information Engineering, Chengdu, China
- Qiang Yang 0017 — Chongqing Jiaotong University, China (and 1 more)
- Qiang Yang 0018 — Hong Kong Polytechnic University (and 1 more)
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2010 – 2019
- 2014
[j2]Qiang Yang, Jian Fu, Raphael Poss, Chris R. Jesshope:
On-chip traffic regulation to reduce coherence protocol cost on a microthreaded many-core architecture with distributed caches. ACM Trans. Embed. Comput. Syst. 13(3s): 103:1-103:21 (2014)- [c6]Jian Fu, Qiang Yang, Raphael Poss, Chris R. Jesshope, Chunyuan Zhang:
Rethread: A Low-Cost Transient Fault Recovery Scheme for Multithreaded Processors. ARES 2014: 88-93 - [c5]Jian Fu, Qiang Yang, Raphael Poss, Chris R. Jesshope, Chunyuan Zhang:
A fault detection mechanism in a Data-flow scheduled Multithreaded processor. DATE 2014: 1-4 - 2013
- [j1]Raphael Poss, Mike Lankamp, Qiang Yang, Jian Fu, Michiel W. van Tol, Muhammad Irfan Uddin, Chris R. Jesshope:
Apple-CORE: Harnessing general-purpose many-cores with hardware concurrency management. Microprocess. Microsystems 37(8-C): 1090-1101 (2013) - [c4]Raphael Poss, Mike Lankamp, Qiang Yang, Jian Fu, Muhammad Irfan Uddin, Chris R. Jesshope:
MGSim - A simulation environment for multi-core research and education. ICSAMOS 2013: 80-87 - [c3]Jian Fu, Qiang Yang, Raphael Poss, Chris R. Jesshope, Chunyuan Zhang:
On-demand thread-level fault detection in a concurrent programming environment. ICSAMOS 2013: 255-262 - [i1]Mike Lankamp, Raphael 'kena' Poss, Qiang Yang, Jian Fu, Muhammad Irfan Uddin, Chris R. Jesshope:
MGSim - Simulation tools for multi-core processor architectures. CoRR abs/1302.1390 (2013) - 2012
- [c2]Raphael Poss, Mike Lankamp, Qiang Yang, Jian Fu, Michiel W. van Tol, Chris R. Jesshope:
Apple-CORE: Microgrids of SVP Cores - Flexible, General-Purpose, Fine-Grained Hardware Concurrency Management. DSD 2012: 501-508 - 2011
- [c1]Qiang Yang, Chris R. Jesshope, Jian Fu:
A Micro Threading Based Concurrency Model for Parallel Computing. IPDPS Workshops 2011: 1668-1674
Coauthor Index
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