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ORCIDKaviraj Chopra
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2010 – 2019
- 2011
[j7]Vineeth Veetil, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester:
Fast Statistical Static Timing Analysis Using Smart Monte Carlo Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(6): 852-865 (2011)- [j6]Cheng Zhuo, Kaviraj Chopra, Dennis Sylvester, David T. Blaauw:
Process Variation and Temperature-Aware Full Chip Oxide Breakdown Reliability Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(9): 1321-1334 (2011) - 2010
- [j5]Ravikishore Gandikota, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester:
Victim Alignment in Crosstalk-Aware Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(2): 261-274 (2010)
2000 – 2009
- 2008
- [b1]Kaviraj Chopra:
Statistical Performance Analysis Optimization of Digital Circuits. University of Michigan, USA, 2008 - [j4]Ashish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David T. Blaauw:
A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(2): 272-285 (2008) - [j3]David T. Blaauw, Kaviraj Chopra, Ashish Srivastava, Louis Scheffer:
Statistical Timing Analysis: From Basic Principles to State of the Art. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(4): 589-607 (2008) - [c14]Brian Cline, Kaviraj Chopra, David T. Blaauw, Andres Torres, Savithri Sundareswaran:
Transistor-Specific Delay Modeling for SSTA. DATE 2008: 592-597 - [c13]Kaviraj Chopra, Cheng Zhuo, David T. Blaauw, Dennis Sylvester:
A statistical approach for full-chip gate-oxide reliability analysis. ICCAD 2008: 698-705 - 2007
- [j2]Rajeev R. Rao, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester:
Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3): 468-479 (2007) - [c12]Ravikishore Gandikota, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester, Murat R. Becer:
Top-k Aggressors Sets in Delay Noise Analysis. DAC 2007: 174-179 - [c11]Ravikishore Gandikota, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester, Murat R. Becer, Joao Geada:
Victim alignment in crosstalk aware timing analysis. ICCAD 2007: 698-704 - [i1]Aseem Agarwal, Kaviraj Chopra, David T. Blaauw:
Statistical Timing Based Optimization using Gate Sizing. CoRR abs/0710.4697 (2007) - 2006
- [j1]Kaviraj Chopra, Sarma B. K. Vrudhula:
Efficient Symbolic Algorithms for Computing the Minimum and Bounded Leakage States. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2820-2832 (2006) - [c10]Rajeev R. Rao, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester:
An efficient static algorithm for computing the soft error rates of combinational circuits. DATE 2006: 164-169 - [c9]Brian Cline, Kaviraj Chopra, David T. Blaauw, Yu Cao:
Analysis and modeling of CD variation for statistical static timing. ICCAD 2006: 60-66 - [c8]Kaviraj Chopra, Bo Zhai, David T. Blaauw, Dennis Sylvester:
A new statistical max operation for propagating skewness in statistical timing analysis. ICCAD 2006: 237-243 - 2005
- [c7]Aseem Agarwal, Kaviraj Chopra, David T. Blaauw, Vladimir Zolotov:
Circuit optimization using statistical static timing analysis. DAC 2005: 321-324 - [c6]David T. Blaauw, Kaviraj Chopra:
CAD tools for variation tolerance. DAC 2005: 766 - [c5]Aseem Agarwal, Kaviraj Chopra, David T. Blaauw:
Statistical Timing Based Optimization using Gate Sizing. DATE 2005: 400-405 - [c4]Kaviraj Chopra, Saumil Shah, Ashish Srivastava, David T. Blaauw, Dennis Sylvester:
Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation. ICCAD 2005: 1023-1028 - 2004
- [c3]Kaviraj Chopra, Sarma B. K. Vrudhula:
Implicit pseudo boolean enumeration algorithms for input vector control. DAC 2004: 767-772 - [c2]Sridhar Dasika, Sarma B. K. Vrudhula, Kaviraj Chopra, R. Srinivasan:
A Framework for Battery-Aware Sensor Management. DATE 2004: 962-967 - [c1]Kaviraj Chopra, Sarma B. K. Vrudhula, Sarvesh Bhardwaj:
Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic. VLSI Design 2004: 240-
Coauthor Index
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