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ORCIDSatoshi Shigematsu
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2020 – today
- 2020
[c20]Kota Shikama, Norio Sato, Atsushi Aratake, Satoshi Shigematsu, Takeshi Sakamoto:
Miniature Optical Connector with Magnetic Physical Contact. OFC 2020: 1-3- [c19]Yuki Arikawa, Takeshi Sakamoto, Satoshi Shigematsu:
Hierarchical Scheduling with FPGA-based Accelerator for Flexible 5G Mobile Networks. VTC Spring 2020: 1-5
2010 – 2019
- 2019
- [j15]Kazunari Kurita
, Takeshi Kadono, Satoshi Shigematsu, Ryo Hirose, Ryosuke Okuyama, Ayumi Onaka-Masada, Hidehiko Okuda, Yoshihiro Koga:
Proximity Gettering Design of Hydrocarbon-Molecular-Ion-Implanted Silicon Wafers Using Dark Current Spectroscopy for CMOS Image Sensors. Sensors 19(9): 2073 (2019) - [c18]Morihiko Minowa, Hiroyuki Seki, Yukihiko Okumura, Satoshi Suyama, Jun Terada, Satoshi Shigematsu, Yasushi Takatori, Hiroaki Asano, Yukio Hirano, Yasushi Yamao, Fumiyuki Adachi, Masataka Nakazawa:
5G R&D Activities for High Capacity Technologies with Ultra High-Density Multi-Band and Multi-Access Layered Cells. VTC Spring 2019: 1-5 - 2018
- [c17]Salah Ibrahim, Toshikazu Hashimoto, Satoshi Shigematsu:
Contention-Less Scheduling-Free Torus Optical Network Comprising Thousands of Nodes. ECOC 2018: 1-3 - [c16]Yuki Arikawa, Takeshi Sakamoto, Shunji Kimura, Satoshi Shigematsu:
Throughput Enhancement with Hardware Accelerated Resource Scheduler in Low-Latency 5G Systems. PIMRC 2018: 1-6 - 2017
- [j14]Kousuke Imamura, Ryota Honda, Yoshifumi Kawamura, Naoki Miura, Masami Urano, Satoshi Shigematsu, Tetsuya Matsumura, Yoshio Matsuda:
A 100-MHz 51.2-Gb/s Packet Lookup Engine with Automatic Table Update Function. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(10): 2123-2134 (2017) - 2016
- [c15]Yuki Arikawa, Hiroyuki Uzawa, Takeshi Sakamoto, Satoshi Shigematsu:
High-speed radio-resource scheduling for 5G ultra-high-density distributed antenna systems. WCSP 2016: 1-5 - 2015
- [j13]Naoki Miura, Akihiko Miyazaki, Junichi Kato, Nobuyuki Tanaka, Satoshi Shigematsu, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata:
Software-Hardware-Cooperative Protocol Processor for Extendable 10G-EPON MAC Chip. IEICE Trans. Electron. 98-C(1): 45-52 (2015) - [c14]Hiroyuki Uzawa, Kazuhiko Terada, Namiko Ikeda, Satoshi Shigematsu:
High-speed sorted-table search scheme for network processing. APCC 2015: 616-620 - [c13]Hiroyuki Uzawa, Yuki Arikawa, Kenji Kawai, Satoshi Shigematsu:
Data transmission scheme for enhancing effective downlink bandwidth in 5G mobile fronthaul with TDM-PON. ECOC 2015: 1-3 - [c12]Yoshifumi Kawamura, Kousuke Imamura, Naoki Miura, Masami Urano, Satoshi Shigematsu, Yoshio Matsuda:
A 100-MHz 51.2-Gb/s packet lookup engine LSI based on missmatch detection circuit combined with linked-list hash table. ISPACS 2015: 351-356 - [c11]Yuki Arikawa, Kenji Kawai, Hiroyuki Uzawa, Satoshi Shigematsu:
Practical resource scheduling in massive-cell deployment for 5G mobile communications systems. ISPACS 2015: 456-461 - 2014
- [c10]Takayoshi Tashiro, Shigeru Kuwano, Jun Terada, Tomoaki Kawamura, Nobuyuki Tanaka, Satoshi Shigematsu, Naoto Yoshimoto:
A novel DBA scheme for TDM-PON based mobile fronthaul. OFC 2014: 1-3 - [c9]Saki Hatta, Nobuyuki Tanaka, Satoshi Shigematsu:
Area-efficient dynamically reconfigurable protocol-processing-hardware for access network communications SoC. ReConFig 2014: 1-6 - 2012
- [j12]Alice Wang, Ken Takeuchi, Tanay Karnik, Maysam Ghovanloo, Satoshi Shigematsu:
Introduction to the Special Issue on the 2011 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 47(1): 3-7 (2012) - [c8]Kazuhiko Terada, Hiroyuki Uzawa, Namiko Ikeda, Satoshi Shigematsu, Nobuyuki Tanaka, Masami Urano:
Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs. FPL 2012: 639-642 - 2010
- [j11]Toshishige Shimamura, Hiroki Morimura, Satoshi Shigematsu, Mamoru Nakanishi, Katsuyuki Machida:
Capacitive-Sensing Circuit Technique for Image Quality Improvement on Fingerprint Sensor LSIs. IEEE J. Solid State Circuits 45(5): 1080-1087 (2010) - [c7]Satoshi Shigematsu, Kazutami Arimoto, Christoph Hagleitner:
Fusion of MEMS and circuits. ISSCC 2010: 526-527
2000 – 2009
- 2008
- [c6]Toshishige Shimamura, Hiroki Morimura, Nobuhiro Shimoyama, Tomomi Sakata, Satoshi Shigematsu, Katsuyuki Machida, Mamoru Nakanishi:
A Fingerprint Sensor with Impedance Sensing for Fraud Detection. ISSCC 2008: 170-171 - 2007
- [j10]Satoshi Shigematsu, Hiroki Morimura, Toshishige Shimamura, Takahiro Hatano, Namiko Ikeda, Yukio Okazaki, Katsuyuki Machida, Mamoru Nakanishi:
Logic and Analog Test Schemes for a Single-Chip Pixel-Parallel Fingerprint Identification LSI. IEICE Trans. Electron. 90-C(10): 1892-1899 (2007) - 2006
- [j9]Satoshi Shigematsu, Koji Fujii, Hiroki Morimura, Takahiro Hatano, Mamoru Nakanishi, Namiko Ikeda, Toshishige Shimamura, Katsuyuki Machida, Yukio Okazaki, Hakaru Kyuragi:
Fingerprint Image Enhancement and Rotation Schemes for a Single-Chip Fingerprint Sensor and Identifier. IEICE Trans. Electron. 89-C(4): 540-550 (2006) - 2005
- [j8]Satoshi Shigematsu, Hiroki Morimura, Katsuyuki Machida, Yukio Okazaki, Hakaru Kyuragi:
Pixel-Parallel Image-Matching Circuit Schemes for a Single-Chip Fingerprint Sensor and Identifier. IEICE Trans. Electron. 88-C(5): 1070-1078 (2005) - 2002
- [j7]Hiroki Morimura, Satoshi Shigematsu, Toshishige Shimamura, Katsuyuki Machida, Hakaru Kyuragi:
A pixel-level automatic calibration circuit scheme for capacitive fingerprint sensor LSIs. IEEE J. Solid State Circuits 37(10): 1300-1306 (2002) - [c5]Koji Fujii, Mamoru Nakanishi, Satoshi Shigematsu, Hiroki Morimura, Takahiro Hatano, Namiko Ikeda, Toshishige Shimamura, Yukio Okazaki, Hakaru Kyuragi:
A 500-dpi cellular-logic processing array for fingerprint-image enhancement and verification. CICC 2002: 261-264 - [c4]Namiko Ikeda, Mamoru Nakanishi, Koji Fujii, Takahiro Hatano, Satoshi Shigematsu, Takuya Adachi, Yukio Okazaki, Hakaru Kyuragi:
Fingerprint Image Enhancement by Pixel-Parallel Processing. ICPR (3) 2002: 752-755 - [c3]Takahiro Hatano, Takuya Adachi, Satoshi Shigematsu, Hiroki Morimura, Shigehiko Onishi, Yukio Okazaki, Hakaru Kyuragi:
A Fingerprint Verification Algorithm Using the Differential Matching Rate. ICPR (3) 2002: 799-802 - 2000
- [j6]Hiroki Morimura, Satoshi Shigematsu, Katsuyuki Machida:
A novel sensor cell architecture and sensing circuit scheme for capacitive fingerprint sensors. IEEE J. Solid State Circuits 35(5): 724-731 (2000)
1990 – 1999
- 1999
- [j5]Satoshi Shigematsu, Hiroki Morimura, Yasuyuki Tanabe, Takuya Adachi, Katsuyuki Machida:
A single-chip fingerprint sensor and identifier. IEEE J. Solid State Circuits 34(12): 1852-1859 (1999) - [c2]Shinichiro Mutoh, Satoshi Shigematsu, Yoshinori Gotoh, Shinsuke Konaka:
Design Method of MTCMOS Power Switch for Low-Voltage High-Speed LSIs. ASP-DAC 1999: 113-116 - [c1]Hiroki Morimura, Satoshi Shigematsu, Shinsuke Konaka:
A shared-bitline SRAM cell architecture for 1-V ultra low-power word-bit configurable macrocells. ISLPED 1999: 12-17 - 1997
- [j4]Satoshi Shigematsu, Shin'ichiro Mutoh, Yasuyuki Matsuya, Yasuyuki Tanabe, Junzo Yamada:
A 1-V high-speed MTCMOS circuit scheme for power-down application circuits. IEEE J. Solid State Circuits 32(6): 861-869 (1997) - [j3]Takakuni Douseki, Satoshi Shigematsu, Junzo Yamada, Mitsuru Harada, Hiroshi Inokawa, Toshiaki Tsuchiya:
A 0.5-V MTCMOS/SIMOX logic gate. IEEE J. Solid State Circuits 32(10): 1604-1609 (1997) - 1996
- [j2]Shinichiro Mutoh, Satoshi Shigematsu, Yasuyuki Matsuya, H. Fukuda, T. Kaneko, Junzo Yamada:
A 1-V multithreshold-voltage CMOS digital signal processor for mobile phone application. IEEE J. Solid State Circuits 31(11): 1795-1802 (1996) - 1995
- [j1]Shin'ichiro Mutoh, Takakuni Douseki, Yasuyuki Matsuya, Takahko Aoki, Satoshi Shigematsu, Junzo Yamada:
1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS. IEEE J. Solid State Circuits 30(8): 847-854 (1995)
Coauthor Index
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