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2020 – today
- 2024
[c18]Maksim Jenihhin, Mahdi Taheri, Natalia Cherezova, Mohammad Hasan Ahmadilivani, Hardi Selg, Artur Jutman, Konstantin Shibin, Anton Tsertov, Sergei Devadze, Rama Mounika Kodamanchili, Ahsan Rafiq, Jaan Raik, Masoud Daneshtalab:
Keynote: Cost-Efficient Reliability for Edge-AI Chips. LATS 2024: 1-2- 2023
- [c17]Konstantin Shibin, Maksim Jenihhin, Artur Jutman, Sergei Devadze, Anton Tsertov:
On-Chip Sensors Data Collection and Analysis for SoC Health Management. DFT 2023: 1-6 - [i1]Konstantin Shibin, Maksim Jenihhin, Artur Jutman, Sergei Devadze, Anton Tsertov:
On-Chip Sensors Data Collection and Analysis for SoC Health Management. CoRR abs/2308.15917 (2023)
2010 – 2019
- 2019
- [c16]Aleksa Damljanovic, Artur Jutman
, Giovanni Squillero, Anton Tsertov:
Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks. ETS 2019: 1-6 - [c15]Aleksa Damljanovic, Artur Jutman, Michele Portolan, Ernesto Sánchez, Giovanni Squillero, Anton Tsertov:
Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL. ITC 2019: 1-8 - 2017
- [c14]Adeboye Stephen Oyeniran, Artjom Jasnetski, Anton Tsertov, Raimund Ubar:
High-level test data generation for software-based self-test in microprocessors. MECO 2017: 1-6 - [c13]Artjom Jasnetski, Raimund Ubar, Anton Tsertov:
Automated software-based self-test generation for microprocessors. MIXDES 2017: 453-458 - [e1]Thomas Hollstein, Jaan Raik, Sergei Kostin, Anton Tsertov, Ian O'Connor, Ricardo Reis:
VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability - 24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, Revised Selected Papers. IFIP Advances in Information and Communication Technology 508, Springer 2017, ISBN 978-3-319-67103-1 [contents] - 2016
- [c12]Boyang Du, Ernesto Sánchez, Matteo Sonza Reorda, Julio Pérez Acle, Anton Tsertov:
FPGA-controlled PCBA power-on self-test using processor's debug features. DDECS 2016: 125-130 - [c11]Artjom Jasnetski, Stephen Adeboye Oyeniran, Anton Tsertov, Mario Schölzel, Raimund Ubar:
High-level modeling and testing of multiple control faults in digital systems. DDECS 2016: 144-149 - [c10]Anton Tsertov, Artur Jutman, Sergei Devadze, Matteo Sonza Reorda, Erik Larsson, Farrokh Ghani Zadegan, Riccardo Cantoro, Mehrdad Montazeri, Rene Krenz-Baath:
A suite of IEEE 1687 benchmark networks. ITC 2016: 1-10 - [c9]Artjom Jasnetski, Raimund Ubar, Anton Tsertov:
On automatic software-based self-test program generation based on high-level decision diagrams. LATS 2016: 177 - 2015
- [c8]Artjom Jasnetski, Jaan Raik, Anton Tsertov, Raimund Ubar:
New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams. DDECS 2015: 251-254 - 2014
- [c7]Artjom Jasnetski, Raimund Ubar, Anton Tsertov, Helena Kruus:
Laboratory framework TEAM for investigating the dependability issues of microprocessor systems. EWME 2014: 80-83 - [c6]Raimund Ubar, Anton Tsertov, Artjom Jasnetski, Marina Brik:
Software-based self-test generation for microprocessors with high-level decision diagrams. LATW 2014: 1-6 - 2013
- [c5]Anton Tsertov, Sergei Devadze, Artur Jutman, Artjom Jasnetski:
On in-system programming of non-volatile memories. MIXDES 2013: 408-413 - 2011
- [c4]Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze:
Automatic SoC Level Test Path Synthesis Based on Partial Functional Models. Asian Test Symposium 2011: 532-538 - [c3]Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze:
SoC and Board Modeling for Processor-Centric Board Testing. DSD 2011: 575-582 - 2010
- [c2]Anton Tsertov, Artur Jutman, Sergei Devadze:
Testing beyond the SoCs in a lego style. EWDTS 2010: 334-338
2000 – 2009
- 2008
- [c1]Artur Jutman, Anton Tsertov, Raimund Ubar:
Calculation of LFSR Seed and Polynomial Pair for BIST Applications. DDECS 2008: 275-278
Coauthor Index
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