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Akira Shikata
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2010 – 2019
- 2019
- [j7]Junhua Shen
, Akira Shikata, Anping Liu, Baozhen Chen
, Frederick Chalifoux:
A 12-Bit 31.1- $\mu$ W 1-MS/s SAR ADC With On-Chip Input-Signal-Independent Calibration Achieving 100.4-dB SFDR Using 256-fF Sampling Capacitance. IEEE J. Solid State Circuits 54(4): 937-947 (2019) - 2018
- [j6]Junhua Shen
, Akira Shikata, Lalinda Fernando, Ned Guthrie
, Baozhen Chen
, Mark Maddox
, Nikhil Mascarenhas, Ron Kapusta
, Michael C. W. Coln
:
A 16-bit 16-MS/s SAR ADC With On-Chip Calibration in 55-nm CMOS. IEEE J. Solid State Circuits 53(4): 1149-1160 (2018) - [c6]Junhua Shen, Akira Shikata, Anping Liu, Frederick Chalifoux:
A 12-Bit 31.1UW 1MS/S SAR ADC with On-Chip Input-Signal-Independent Calibration Achieving 100.4DB SFDR Using 256FF Sampling Capacitance. VLSI Circuits 2018: 91-92 - 2015
- [j5]Kentaro Yoshioka
, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro:
An 8 bit 0.3-0.8 V 0.2-40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 23(2): 356-368 (2015) - 2014
- [c5]Kentaro Yoshioka
, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro:
An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique. ASP-DAC 2014: 31-32 - 2013
- [j4]Akira Shikata, Ryota Sekimoto, Kentaro Yoshioka
, Tadahiro Kuroda, Hiroki Ishikuro:
A 4-10 bit, 0.4-1 V Power Supply, Power Scalable Asynchronous SAR-ADC in 40 nm-CMOS with Wide Supply Voltage Range SAR Controller. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(2): 443-452 (2013) - [j3]Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka
, Tadahiro Kuroda, Hiroki Ishikuro:
An Adaptive DAC Settling Waiting Time Optimized Ultra Low Voltage Asynchronous SAR ADC in 40 nm CMOS. IEICE Trans. Electron. 96-C(6): 820-827 (2013) - [j2]Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka
, Tadahiro Kuroda, Hiroki Ishikuro:
A 0.5-V 5.2-fJ/Conversion-Step Full Asynchronous SAR ADC With Leakage Power Reduction Down to 650 pW by Boosted Self-Power Gating in 40-nm CMOS. IEEE J. Solid State Circuits 48(11): 2628-2636 (2013) - [c4]Kentaro Yoshioka
, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro:
A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC. ASP-DAC 2013: 111-112 - 2012
- [j1]Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro:
A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS. IEEE J. Solid State Circuits 47(4): 1022-1030 (2012) - [c3]Kentaro Yoshioka
, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro:
An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator. ESSCIRC 2012: 381-384 - 2011
- [c2]Ryota Sekimoto, Akira Shikata, Tadahiro Kuroda, Hiroki Ishikuro:
A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator. ESSCIRC 2011: 471-474 - 2010
- [c1]Akira Shikata, Ryota Sekimoto, Hiroki Ishikuro:
A 0.5V 65nm-CMOS single phase clocked bootstrapped switch with rise time accelerator. APCCAS 2010: 1015-1018
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