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Svilen Kanev
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2020 – today
- 2024
- [c12]Zhuangzhuang Zhou
, Vaibhav Gogte
, Nilay Vaish
, Chris Kennelly
, Patrick Xia
, Svilen Kanev
, Tipp Moseley
, Christina Delimitrou
, Parthasarathy Ranganathan
:
Characterizing a Memory Allocator at Warehouse Scale. ASPLOS (3) 2024: 192-206 - 2023
- [c11]Sagar Karandikar
, Aniruddha N. Udipi
, Junsun Choi
, Joonho Whangbo
, Jerry Zhao
, Svilen Kanev
, Edwin Lim
, Jyrki Alakuijala
, Vrishab Madduri
, Yakun Sophia Shao
, Borivoje Nikolic
, Krste Asanovic
, Parthasarathy Ranganathan
:
CDPU: Co-designing Compression and Decompression Processing Units for Hyperscale Systems. ISCA 2023: 39:1-39:17 - [c10]Nayana Prasad Nagendra
, Bhargav Reddy Godala
, Ishita Chaturvedi
, Atmn Patel
, Svilen Kanev
, Tipp Moseley
, Jared Stark
, Gilles A. Pokam
, Simone Campanoni
, David I. August
:
EMISSARY: Enhanced Miss Awareness Replacement Policy for L2 Instruction Caching. ISCA 2023: 62:1-62:13 - 2020
- [j5]Nayana Prasad Nagendra, Grant Ayers, David I. August, Hyoun Kyu Cho, Svilen Kanev, Christos Kozyrakis, Trivikram Krishnamurthy, Heiner Litz, Tipp Moseley, Parthasarathy Ranganathan:
AsmDB: Understanding and Mitigating Front-End Stalls in Warehouse-Scale Computers. IEEE Micro 40(3): 56-63 (2020)
2010 – 2019
- 2019
- [c9]Grant Ayers, Nayana Prasad Nagendra, David I. August, Hyoun Kyu Cho, Svilen Kanev, Christos Kozyrakis, Trivikram Krishnamurthy, Heiner Litz, Tipp Moseley, Parthasarathy Ranganathan:
AsmDB: understanding and mitigating front-end stalls in warehouse-scale computers. ISCA 2019: 462-473 - 2017
- [j4]Simone Campanoni, Kevin Brownell, Svilen Kanev, Timothy M. Jones
, Gu-Yeon Wei, David M. Brooks:
Automatically accelerating non-numerical programs by architecture-compiler co-design. Commun. ACM 60(12): 88-97 (2017) - [j3]Xin Zhan, Reza Azimi, Svilen Kanev, David M. Brooks, Sherief Reda:
CARB: A C-State Power Management Arbiter for Latency-Critical Workloads. IEEE Comput. Archit. Lett. 16(1): 6-9 (2017) - [c8]Svilen Kanev, Sam Likun Xi, Gu-Yeon Wei, David M. Brooks:
Mallacc: Accelerating Memory Allocation. ASPLOS 2017: 33-45 - 2016
- [j2]Svilen Kanev, Juan Pablo Darago, Kim M. Hazelwood, Parthasarathy Ranganathan, Tipp Moseley, Gu-Yeon Wei, David M. Brooks:
Profiling a Warehouse-Scale Computer. IEEE Micro 36(3): 54-59 (2016) - 2015
- [c7]Svilen Kanev, Juan Pablo Darago, Kim M. Hazelwood, Parthasarathy Ranganathan, Tipp Moseley, Gu-Yeon Wei, David M. Brooks:
Profiling a warehouse-scale computer. ISCA 2015: 158-169 - 2014
- [c6]Svilen Kanev, Kim M. Hazelwood, Gu-Yeon Wei, David M. Brooks:
Tradeoffs between power management and tail latency in warehouse-scale applications. IISWC 2014: 31-40 - [c5]Simone Campanoni, Kevin Brownell, Svilen Kanev, Timothy M. Jones
, Gu-Yeon Wei, David M. Brooks:
HELIX-RC: An architecture-compiler co-design for automatic parallelization of irregular programs. ISCA 2014: 217-228 - 2013
- [c4]Xuan Zhang
, Tao Tong, Svilen Kanev, Sae Kyu Lee, Gu-Yeon Wei, David M. Brooks:
Characterizing and evaluating voltage noise in multi-core near-threshold processors. ISLPED 2013: 82-87 - 2012
- [c3]Svilen Kanev, Gu-Yeon Wei, David M. Brooks:
XIOSim: power-performance modeling of mobile x86 cores. ISLPED 2012: 267-272 - 2011
- [j1]Vijay Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael D. Smith, Gu-Yeon Wei, David M. Brooks:
Voltage Noise in Production Processors. IEEE Micro 31(1): 20-28 (2011) - [c2]Svilen Kanev, Robert Cohn:
Portable trace compression through instruction interpretation. ISPASS 2011: 107-116 - 2010
- [c1]Vijay Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael D. Smith, Gu-Yeon Wei, David M. Brooks:
Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling. MICRO 2010: 77-88
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last updated on 2024-05-06 20:25 CEST by the dblp team
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