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Jae-Cheol Son
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2010 – 2019
- 2017
- [j3]Wisam Kadry, Dmitry Krestyashyn, Arkadiy Morgenshtein, Amir Nahir, Vitali Sokhin, Jin Sung Park, Sung-Boem Park, Wookyeong Jeong, Jae-Cheol Son:
Test Generation Methods for Utilization Improvement of Hardware-Accelerated Simulation Platforms. IEEE Des. Test 34(1): 65-76 (2017) - 2015
- [c5]Wisam Kadry, Dmitry Krestyashyn, Arkadiy Morgenshtein, Amir Nahir, Vitali Sokhin, Jin Sung Park, Sung-Boem Park, Wookyeong Jeong, Jae-Cheol Son:
Comparative study of test generation methods for simulation accelerators. DATE 2015: 321-324 - 2013
- [c4]Min-Su Kim, Hyoungwook Lee, Jin-Soo Park, Chunghee Kim, Juhyun Kang, Ken Shin, Emil Kagramanyan, Gunok Jung, Ukrae Cho, Youngmin Shin, Jae-Cheol Son:
Scan-controlled pulse flip-flops for mobile application processors. ISCAS 2013: 769-772 - [c3]Youngmin Shin, Ken Shin, Prashant Kenkare, Rajesh Kashyap, Hoi-Jin Lee, Dongjoo Seo, Brian Millar, Yohan Kwon, Ravi Iyengar, Min-Su Kim, Ahsan Chowdhury, Sung-il Bae, Inpyo Hong, Wookyeong Jeong, Aaron Lindner, Ukrae Cho, Keith Hawkins, Jae-Cheol Son, Seung Ho Hwang:
28nm high- metal-gate heterogeneous quad-core CPUs for high-performance and energy-efficient mobile application processor. ISSCC 2013: 154-155 - 2012
- [j2]Hoi-Jin Lee, Jong-Woo Kim, Tae Hee Han, Jae-Cheol Son, Jeong-Taek Kong, Bai-Sun Kong:
Low-power dual-supply clock networks with clock gating and frequency doubling. IEICE Electron. Express 9(6): 502-508 (2012) - [c2]Se-Hyun Yang, Seogjun Lee, Jae Young Lee, Jeonglae Cho, Hoi-Jin Lee, Dongsik Cho, Junghun Heo, Sunghoon Cho, Youngmin Shin, Sunghee Yun, Euiseok Kim, Ukrae Cho, Edward Pyo, Man Hyuk Park, Jae-Cheol Son, Chinhyun Kim, Jeongnam Youn, Youngki Chung, Sungho Park, Seung Ho Hwang:
A 32nm high-k metal gate application processor with GHz multi-core CPU. ISSCC 2012: 214-216 - 2011
- [c1]Rahul Singh, Jae-Cheol Son, Ukrae Cho, Gunok Jung, Min-Su Kim, Hyoungwook Lee, Suhwan Kim:
A static-switching pulse domino technique for statistical power reduction of wide fan-in dynamic gates. ACM Great Lakes Symposium on VLSI 2011: 127-132 - 2010
- [j1]Gunok Jung, Gi-Ho Park, Ukrae Cho, Jae-Cheol Son:
Fully digital clock frequency doubler. IEICE Electron. Express 7(6): 416-420 (2010)
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