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Shahar Kvatinsky
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2020 – today
- 2024
- [j40]Minhui Zou
, Zhenhua Zhu, Tzofnat Greenberg-Toledo
, Orian Leitersdorf
, Jiang Li
, Junlong Zhou
, Yu Wang
, Nan Du, Shahar Kvatinsky
:
TDPP: 2-D Permutation-Based Protection of Memristive Deep Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(3): 742-755 (2024) - [j39]Henriette Padberg
, Amir Regev, Giuseppe Piccolboni, Alessandro Bricalli, Gabriel Molas
, Jean-Francois Nodin, Shahar Kvatinsky
:
Experimental Demonstration of Non-Stateful In-Memory Logic With 1T1R OxRAM Valence Change Mechanism Memristors. IEEE Trans. Circuits Syst. II Express Briefs 71(1): 395-399 (2024) - [j38]Ben Perach
, Ronny Ronen
, Benny Kimelfeld
, Shahar Kvatinsky
:
Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics. IEEE Trans. Emerg. Top. Comput. 12(1): 7-22 (2024) - [c51]Jiang Li, Yijun Cui, Chenghua Wang, Weiqiang Liu, Shahar Kvatinsky:
A Concealable RRAM Physical Unclonable Function Compatible with In-Memory Computing. DATE 2024: 1-6 - [c50]Arjun Tyagi, Shahar Kvatinsky:
Assessing the Performance of Stateful Logic in 1-Selector-1-RRAM Crossbar Arrays. ISCAS 2024: 1-5 - [c49]Noa Aflalo, Eilam Yalon, Shahar Kvatinsky:
Bitwise Logic Using Phase Change Memory Devices Based on the Pinatubo Architecture. VLSID 2024: 583-586 - [i38]Sariel Hodisan, Shahar Kvatinsky:
Transimpedance Amplifier with Automatic Gain Control Based on Memristors for Optical Signal Acquisition. CoRR abs/2405.02169 (2024) - [i37]Loai Danial, Kanishka Sharma, Shahar Kvatinsky:
A Pipelined Memristive Neural Network Analog-to-Digital Converter. CoRR abs/2406.02197 (2024) - [i36]Arjun Tyagi, Shahar Kvatinsky:
Assessing the Performance of Stateful Logic in 1-Selector-1-RRAM Crossbar Arrays. CoRR abs/2407.10466 (2024) - 2023
- [j37]Orian Leitersdorf, Dean Leitersdorf, Jonathan Gal, Mor M. Dahan, Ronny Ronen, Shahar Kvatinsky:
AritPIM: High-Throughput In-Memory Arithmetic. IEEE Trans. Emerg. Top. Comput. 11(3): 720-735 (2023) - [j36]Marcel Khalifa
, Barak Hoffer
, Orian Leitersdorf
, Robert Hanhan
, Ben Perach
, Leonid Yavits
, Shahar Kvatinsky
:
ClaPIM: Scalable Sequence Classification Using Processing-in-Memory. IEEE Trans. Very Large Scale Integr. Syst. 31(9): 1347-1357 (2023) - [c48]Ben Perach, Ronny Ronen, Shahar Kvatinsky:
On Consistency for Bulk-Bitwise Processing-in-Memory. HPCA 2023: 705-717 - [c47]Ben Perach, Ronny Ronen, Shahar Kvatinsky:
Accelerating Relational Database Analytical Processing with Bulk-Bitwise Processing-in-Memory. NEWCAS 2023: 1-5 - [c46]Ben Perach, Ronny Ronen, Shahar Kvatinsky:
Enabling Relational Database Analytical Processing in Bulk-Bitwise Processing-In-Memory. SOCC 2023: 1-6 - [i35]Ben Perach, Ronny Ronen, Shahar Kvatinsky:
Enabling Relational Database Analytical Processing in Bulk-Bitwise Processing-In-Memory. CoRR abs/2302.01675 (2023) - [i34]Marcel Khalifa, Barak Hoffer, Orian Leitersdorf, Robert Hanhan, Ben Perach, Leonid Yavits, Shahar Kvatinsky:
ClaPIM: Scalable Sequence CLAssification using Processing-In-Memory. CoRR abs/2302.08284 (2023) - [i33]Orian Leitersdorf, Yahav Boneh, Gonen Gazit, Ronny Ronen, Shahar Kvatinsky:
FourierPIM: High-Throughput In-Memory Fast Fourier Transform and Polynomial Multiplication. CoRR abs/2304.02336 (2023) - [i32]Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky:
ConvPIM: Evaluating Digital Processing-in-Memory through Convolutional Neural Network Acceleration. CoRR abs/2305.04122 (2023) - [i31]Ben Perach, Ronny Ronen, Shahar Kvatinsky:
Accelerating Relational Database Analytical Processing with Bulk-Bitwise Processing-in-Memory. CoRR abs/2307.00658 (2023) - [i30]Ben Perach, Shahar Kvatinsky:
An Asynchronous and Low-Power True Random Number Generator using STT-MTJ. CoRR abs/2307.14476 (2023) - [i29]Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky:
CUDA-PIM: End-to-End Integration of Digital Processing-in-Memory from High-Level C++ to Microarchitectural Design. CoRR abs/2308.14007 (2023) - [i28]Minhui Zou, Zhenhua Zhu, Tzofnat Greenberg-Toledo, Orian Leitersdorf, Jiang Li, Junlong Zhou, Yu Wang, Nan Du, Shahar Kvatinsky:
TDPP: Two-Dimensional Permutation-Based Protection of Memristive Deep Neural Networks. CoRR abs/2310.06989 (2023) - [i27]Henriette Padberg, Amir Regev, Giuseppe Piccolboni, Alessandro Bricalli, Gabriel Molas, Jean-François Nodin, Shahar Kvatinsky:
Experimental Demonstration of Non-Stateful In-Memory Logic with 1T1R OxRAM Valence Change Mechanism Memristors. CoRR abs/2310.16843 (2023) - 2022
- [j35]Wei Wang
, Barak Hoffer, Tzofnat Greenberg-Toledo, Yang Li, Minhui Zou, Eric Herbelin, Ronny Ronen, Xiaoxin Xu, Yulin Zhao, Jianguo Yang, Shahar Kvatinsky:
Efficient Training of the Memristive Deep Belief Net Immune to Non-Idealities of the Synaptic Devices. Adv. Intell. Syst. 4(5) (2022) - [j34]Ronny Ronen, Adi Eliahu, Orian Leitersdorf
, Natan Peled, Kunal Korgaonkar, Anupam Chattopadhyay, Ben Perach, Shahar Kvatinsky:
The Bitlet Model: A Parameterized Analytical Model to Compare PIM and CPU Systems. ACM J. Emerg. Technol. Comput. Syst. 18(2): 43:1-43:29 (2022) - [j33]Mor M. Dahan
, Evelyn T. Breyer
, Stefan Slesazeck
, Thomas Mikolajick
, Shahar Kvatinsky
:
C-AND: Mixed Writing Scheme for Disturb Reduction in 1T Ferroelectric FET Memory. IEEE Trans. Circuits Syst. I Regul. Pap. 69(4): 1595-1605 (2022) - [j32]Orian Leitersdorf
, Ronny Ronen
, Shahar Kvatinsky
:
MultPIM: Fast Stateful Multiplication for Processing-in-Memory. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1647-1651 (2022) - [j31]Issa Salameh
, Eby G. Friedman
, Shahar Kvatinsky
:
Superconductive Logic Using 2ϕ - Josephson Junctions With Half Flux Quantum Pulses. IEEE Trans. Circuits Syst. II Express Briefs 69(5): 2533-2537 (2022) - [c45]Aharon Gero
, Mohammed Ali Hadish, Shahar Kvatinsky:
Undergraduate Students' Attitudes Toward an Engineering Course that Integrates Several Levels of Abstraction. ICL (2) 2022: 491-497 - [c44]Orian Leitersdorf
, Ronny Ronen, Shahar Kvatinsky:
MatPIM: Accelerating Matrix Operations with Memristive Stateful Logic. ISCAS 2022: 215-219 - [c43]Minhui Zou, Junlong Zhou, Xiaotong Cui, Wei Wang
, Shahar Kvatinsky:
Enhancing Security of Memristor Computing System Through Secure Weight Mapping. ISVLSI 2022: 182-187 - [c42]Batel Oved, Orian Leitersdorf
, Ronny Ronen, Shahar Kvatinsky:
HashPIM: High-Throughput SHA-3 via Memristive Digital Processing-in-Memory. MOCAST 2022: 1-4 - [i26]Wei Wang, Loai Danial, Eric Herbelin, Barak Hoffer, Batel Oved, Tzofnat Greenberg-Toledo, Evgeny Pikhay, Yakov Roizin, Shahar Kvatinsky:
Physical based compact model of Y-Flash memristor for neuromorphic computation. CoRR abs/2202.10228 (2022) - [i25]Wei Wang, Barak Hoffer, Tzofnat Greenberg-Toledo, Yang Li, Minhui Zou, Eric Herbelin, Ronny Ronen, Xiaoxin Xu, Yulin Zhao, Jianguo Yang, Shahar Kvatinsky:
Efficient Training of the Memristive Deep Belief Net Immune to Non-Idealities of the Synaptic Devices. CoRR abs/2203.07884 (2022) - [i24]Wei Wang, Loai Danial, Yang Li, Eric Herbelin, Evgeny Pikhay, Yakov Roizin, Barak Hoffer, Zhongrui Wang, Shahar Kvatinsky:
Memristive deep belief neural network by silicon synapses. CoRR abs/2203.09046 (2022) - [i23]Ben Perach, Ronny Ronen, Benny Kimelfeld, Shahar Kvatinsky:
PIMDB: Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics. CoRR abs/2203.10486 (2022) - [i22]Mor M. Dahan, Evelyn T. Breyer, Stefan Slesazeck, Thomas Mikolajick, Shahar Kvatinsky:
C-AND: Mixed Writing Scheme for Disturb Reduction in 1T Ferroelectric FET Memory. CoRR abs/2205.12061 (2022) - [i21]Batel Oved, Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky:
HashPIM: High-Throughput SHA-3 via Memristive Digital Processing-in-Memory. CoRR abs/2205.13559 (2022) - [i20]Shahar Kvatinsky:
Making Real Memristive Processing-in-Memory Faster and Reliable. CoRR abs/2205.14584 (2022) - [i19]Marcel Khalifa, Rotem Ben Hur, Ronny Ronen, Orian Leitersdorf, Leonid Yavits, Shahar Kvatinsky:
FiltPIM: In-Memory Filter for DNA Sequencing. CoRR abs/2205.15140 (2022) - [i18]Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky:
PartitionPIM: Practical Memristive Partitions for Fast Processing-in-Memory. CoRR abs/2206.04200 (2022) - [i17]Orian Leitersdorf, Dean Leitersdorf, Jonathan Gal, Mor M. Dahan, Ronny Ronen, Shahar Kvatinsky:
AritPIM: High-Throughput In-Memory Arithmetic. CoRR abs/2206.04218 (2022) - [i16]Minhui Zou, Junlong Zhou, Xiaotong Cui, Wei Wang, Shahar Kvatinsky:
Enhancing Security of Memristor Computing System Through Secure Weight Mapping. CoRR abs/2206.14498 (2022) - [i15]Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky:
MatPIM: Accelerating Matrix Operations with Memristive Stateful Logic. CoRR abs/2206.15165 (2022) - [i14]Barak Hoffer, Shahar Kvatinsky:
Performing Stateful Logic Using Spin-Orbit Torque (SOT) MRAM. CoRR abs/2208.00741 (2022) - [i13]Adi Eliahu, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky:
abstractPIM: A Technology Backward-Compatible Compilation Flow for Processing-In-Memory. CoRR abs/2208.14472 (2022) - [i12]Ben Perach, Ronny Ronen, Shahar Kvatinsky:
On Consistency for Bulk-Bitwise Processing-in-Memory. CoRR abs/2211.07542 (2022) - [i11]Minhui Zou, Nan Du, Shahar Kvatinsky:
Review of security techniques for memristor computing systems. CoRR abs/2212.09347 (2022) - [i10]Barak Hoffer, Nicolás Wainstein, Christopher M. Neumann, Eric Pop
, Eilam Yalon, Shahar Kvatinsky:
Stateful Logic using Phase Change Memory. CoRR abs/2212.14377 (2022) - 2021
- [j30]Dalibor Biolek, Zdenek Kolka, Viera Biolková, Zdenek Biolek, Shahar Kvatinsky:
(V)TEAM for SPICE Simulation of Memristive Devices With Improved Numerical Performance. IEEE Access 9: 30242-30255 (2021) - [j29]Adi Eliahu, Ronny Ronen, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky:
multiPULPly: A Multiplication Engine for Accelerating Neural Networks on Ultra-low-power Architectures. ACM J. Emerg. Technol. Comput. Syst. 17(2): 24:1-24:27 (2021) - [j28]Minhui Zou
, Junlong Zhou, Jin Sun
, Chengliang Wang
, Shahar Kvatinsky
:
Improving Efficiency and Lifetime of Logic-in-Memory by Combining IMPLY and MAGIC Families. J. Syst. Archit. 119: 102232 (2021) - [j27]Nicolás Wainstein
, Gina C. Adam
, Eilam Yalon
, Shahar Kvatinsky
:
Radiofrequency Switches Based on Emerging Resistive Memory Technologies - A Survey. Proc. IEEE 109(1): 77-95 (2021) - [c41]Orian Leitersdorf
, Ben Perach, Ronny Ronen, Shahar Kvatinsky:
Efficient Error-Correcting-Code Mechanism for High-Throughput Memristive Processing-in-Memory. DAC 2021: 199-204 - [c40]Marcel Khalifa
, Rotem Ben Hur, Ronny Ronen, Orian Leitersdorf
, Leonid Yavits, Shahar Kvatinsky:
FiltPIM: In-Memory Filter for DNA Sequencing. ICECS 2021: 1-4 - [c39]Orian Leitersdorf
, Ronny Ronen, Shahar Kvatinsky:
Making Memristive Processing-in-Memory Reliable. ICECS 2021: 1-6 - [e1]Andrea Calimera
, Pierre-Emmanuel Gaillardon
, Kunal Korgaonkar
, Shahar Kvatinsky
, Ricardo Reis
:
VLSI-SoC: Design Trends - 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers. IFIP Advances in Information and Communication Technology 621, Springer 2021, ISBN 978-3-030-81640-7 [contents] - [i9]Orian Leitersdorf
, Ben Perach, Ronny Ronen, Shahar Kvatinsky:
Efficient Error-Correcting-Code Mechanism for High-Throughput Memristive Processing-in-Memory. CoRR abs/2105.04212 (2021) - [i8]Ronny Ronen, Adi Eliahu, Orian Leitersdorf
, Natan Peled, Kunal Korgaonkar, Anupam Chattopadhyay, Ben Perach, Shahar Kvatinsky:
The Bitlet Model: A Parameterized Analytical Model to Compare PIM and CPU Systems. CoRR abs/2107.10308 (2021) - [i7]Orian Leitersdorf
, Ronny Ronen, Shahar Kvatinsky:
MultPIM: Fast Stateful Multiplication for Processing-in-Memory. CoRR abs/2108.13378 (2021) - [i6]Orian Leitersdorf
, Ronny Ronen, Shahar Kvatinsky:
Making Memristive Processing-in-Memory Reliable. CoRR abs/2109.09687 (2021) - 2020
- [j26]Hanna Abo Hanna
, Loai Danial, Shahar Kvatinsky
, Ramez Daniel:
Cytomorphic Electronics With Memristors for Modeling Fundamental Genetic Circuits. IEEE Trans. Biomed. Circuits Syst. 14(3): 386-401 (2020) - [j25]Rotem Ben Hur
, Ronny Ronen
, Ameer Haj Ali
, Debjyoti Bhattacharjee
, Adi Eliahu
, Natan Peled, Shahar Kvatinsky
:
SIMPLER MAGIC: Synthesis and Mapping of In-Memory Logic Executed in a Single Row to Improve Throughput. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2434-2447 (2020) - [c38]Loai Danial, Vasu Gupta
, Evgeny Pikhay, Yakov Roizin, Shahar Kvatinsky:
Modeling a Floating-Gate Memristive Device for Computer Aided Design of Neuromorphic Computing. DATE 2020: 472-477 - [c37]Vishal Gupta
, Danilo Pellegrini, Saurabh Khandelwal, Abusaleh M. Jabir, Shahar Kvatinsky, Eugenio Martinelli, Corrado Di Natale, Marco Ottavi
:
Sensing with Memristive Complementary Resistive Switch: Modelling and Simulations. DFT 2020: 1-6 - [c36]Loai Danial, Shahar Kvatinsky:
Breaking the Conversion Wall in Mixed-Signal Systems Using Neuromorphic Data Converters. ECCTD 2020: 1-4 - [c35]Debjyoti Bhattacharjee
, Anupam Chattopadhyay, Srijit Dutta, Ronny Ronen, Shahar Kvatinsky:
CONTRA: Area-Constrained Technology Mapping Framework For Memristive Memory Processing Unit. ICCAD 2020: 150:1-150:9 - [c34]Loai Danial, Kanishka Sharma, Shahar Kvatinsky:
A Pipelined Memristive Neural Network Analog-to-Digital Converter. ISCAS 2020: 1-5 - [c33]Ben Perach, Shahar Kvatinsky:
An Asynchronous and Low-Power True Random Number Generator using STT-MTJ. ISCAS 2020: 1 - [c32]Adi Eliahu, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky:
abstractPIM: Bridging the Gap Between Processing-In-Memory Technology and Instruction Set Architecture. VLSI-SOC 2020: 28-33 - [c31]Natan Peled, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky:
X-MAGIC: Enhancing PIM Using Input Overwriting Capabilities. VLSI-SOC 2020: 64-69 - [c30]Adi Eliahu, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky:
abstractPIM: A Technology Backward-Compatible Compilation Flow for Processing-In-Memory. VLSI-SoC (Selected Papers) 2020: 343-361 - [i5]Debjyoti Bhattacharjee, Anupam Chattopadhyay, Srijit Dutta, Ronny Ronen, Shahar Kvatinsky:
CONTRA: Area-Constrained Technology Mapping Framework For Memristive Memory Processing Unit. CoRR abs/2009.00881 (2020)
2010 – 2019
- 2019
- [j24]Nishil Talati, Heonjae Ha, Ben Perach, Ronny Ronen, Shahar Kvatinsky:
CONCEPT: A Column-Oriented Memory Controller for Efficient Memory and PIM Operations in RRAM. IEEE Micro 39(1): 33-43 (2019) - [j23]Nimrod Wald, Shahar Kvatinsky:
Understanding the influence of device, circuit and environmental variations on real processing in memristive memory using Memristor Aided Logic. Microelectron. J. 86: 22-33 (2019) - [j22]Misbah Ramadan, Nicolás Wainstein, Ran Ginosar, Shahar Kvatinsky:
Adaptive programming in multi-level cell ReRAM. Microelectron. J. 90: 169-180 (2019) - [j21]Edouard Giacomin
, Tzofnat Greenberg-Toledo
, Shahar Kvatinsky
, Pierre-Emmanuel Gaillardon
:
A Robust Digital RRAM-Based Convolutional Block for Low-Power Image Processing and Learning Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(2): 643-654 (2019) - [j20]Tzofnat Greenberg-Toledo
, Roee Mazor, Ameer Haj Ali
, Shahar Kvatinsky:
Supporting the Momentum Training Algorithm Using a Memristor-Based Synapse. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(4): 1571-1583 (2019) - [j19]Ben Perach
, Shahar Kvatinsky
:
An Asynchronous and Low-Power True Random Number Generator Using STT-MTJ. IEEE Trans. Very Large Scale Integr. Syst. 27(11): 2473-2484 (2019) - [c29]Shahar Kvatinsky:
Real Processing-in-Memory with Memristive Memory Processing Unit (mMPU). ASAP 2019: 142-148 - [c28]Loai Danial, Kanishka Sharma, Shivansh Dwivedi, Shahar Kvatinsky:
Logarithmic Neural Network Data Converters using Memristors for Biomedical Applications. BioCAS 2019: 1-4 - [c27]Ben Perach
, Shahar Kvatinsky:
STT-ANGIE: Asynchronous True Random Number GEnerator Using STT-MTJ. DATE 2019: 264-267 - [c26]Jeffry Louis, Barak Hoffer, Shahar Kvatinsky:
Performing Memristor-Aided Logic (MAGIC) using STT-MRAM. ICECS 2019: 787-790 - [c25]Marco Ottavi
, Vishal Gupta
, Saurabh Khandelwal
, Shahar Kvatinsky, Jimson Mathew, Eugenio Martinelli, Abusaleh M. Jabir:
The Missing Applications Found: Robust Design Techniques and Novel Uses of Memristors. IOLTS 2019: 159-164 - [c24]Loai Danial, Sidharth Thomas, Shahar Kvatinsky:
Delta-Sigma Modulation Neurons for High-Precision Training of Memristive Synapses in Deep Neural Networks. ISCAS 2019: 1-5 - [c23]Nicolás Wainstein, Tamir Tsabari, Yarden Goldin, Eilam Yalon
, Shahar Kvatinsky:
A Dual-Band CMOS Low-Noise Amplifier using Memristor-Based Tunable Inductors. ISVLSI 2019: 290-295 - [c22]Shahar Kvatinsky:
Real Processing-In-Memory with Memristive Memory Processing Unit. SPACE 2019: 5-8 - [c21]João Vieira, Edouard Giacomin
, Yasir Mahmood Qureshi, Marina Zapater, Xifan Tang, Shahar Kvatinsky, David Atienza, Pierre-Emmanuel Gaillardon:
A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories. VLSI-SoC 2019: 160-165 - [c20]João Vieira, Edouard Giacomin, Yasir Mahmood Qureshi, Marina Zapater, Xifan Tang, Shahar Kvatinsky, David Atienza, Pierre-Emmanuel Gaillardon:
Accelerating Inference on Binary Neural Networks with Digital RRAM Processing. VLSI-SoC (Selected Papers) 2019: 257-278 - [p1]John Reuben, Nishil Talati, Nimrod Wald, Rotem Ben Hur, Ameer Haj Ali, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky:
A Taxonomy and Evaluation Framework for Memristive Logic. Handbook of Memristor Networks 2019: 1065-1099 - [i4]Kunal Korgaonkar, Ronny Ronen, Anupam Chattopadhyay, Shahar Kvatinsky:
The Bitlet Model: Defining a Litmus Test for the Bitwise Processing-in-Memory Paradigm. CoRR abs/1910.10234 (2019) - [i3]Tzofnat Greenberg-Toledo, Ben Perach, Daniel Soudry, Shahar Kvatinsky:
MTJ-Based Hardware Synapse Design for Quantized Deep Neural Networks. CoRR abs/1912.12636 (2019) - 2018
- [j18]Loai Danial
, Nicolás Wainstein
, Shraga Kraus, Shahar Kvatinsky:
DIDACTIC: A Data-Intelligent Digital-to-Analog Converter with a Trainable Integrated Circuit using Memristors. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(1): 146-158 (2018) - [j17]Alexander Dozortsev, Israel Goldshtein
, Shahar Kvatinsky:
Analysis of the row grounding technique in a memristor-based crossbar array. Int. J. Circuit Theory Appl. 46(1): 122-137 (2018) - [j16]Ameer Haj Ali, Rotem Ben Hur, Nimrod Wald, Ronny Ronen, Shahar Kvatinsky:
Not in Name Alone: A Memristive Memory Processing Unit for Real In-Memory Processing. IEEE Micro 38(5): 13-21 (2018) - [j15]Nicolás Wainstein
, Shahar Kvatinsky:
TIME - Tunable Inductors Using MEmristors. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(5): 1505-1515 (2018) - [j14]Ameer Haj Ali
, Rotem Ben Hur, Nimrod Wald, Ronny Ronen, Shahar Kvatinsky:
IMAGING: In-Memory AlGorithms for Image processiNG. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(12): 4258-4271 (2018) - [j13]Loai Danial
, Nicolás Wainstein, Shraga Kraus, Shahar Kvatinsky
:
Breaking Through the Speed-Power-Accuracy Tradeoff in ADCs Using a Memristive Neuromorphic Architecture. IEEE Trans. Emerg. Top. Comput. Intell. 2(5): 396-409 (2018) - [c19]Nishil Talati, Ameer Haj Ali, Rotem Ben Hur, Nimrod Wald, Ronny Ronen, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky:
Practical challenges in delivering the promises of real processing-in-memory machines. DATE 2018: 1628-1633 - [c18]Ameer Haj Ali, Rotem Ben Hur, Nimrod Wald, Shahar Kvatinsky:
Efficient Algorithms for In-Memory Fixed Point Multiplication Using MAGIC. ISCAS 2018: 1-5 - [c17]Loai Danial, Shahar Kvatinsky:
Real-Time Trainable Data Converters for General Purpose Applications. NANOARCH 2018: 34-36 - 2017
- [j12]Ardavan Pedram, Stephen Richardson, Mark Horowitz, Sameh Galal, Shahar Kvatinsky:
Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era. IEEE Des. Test 34(2): 39-50 (2017) - [c16]Hanna Abo Hanna, Loai Danial, Shahar Kvatinsky, Ramez Daniel:
Modeling biochemical reactions and gene networks with memristors. BioCAS 2017: 1-4 - [c15]Said Hamdioui, Shahar Kvatinsky, Gert Cauwenberghs
, Lei Xie, Nimrod Wald, Siddharth Joshi, Hesham Mostafa Elsayed, Henk Corporaal, Koen Bertels:
Memristor for computing: Myth or reality? DATE 2017: 722-731 - [c14]Leonid Azriel, Shahar Kvatinsky:
Towards a memristive hardware secure hash function (MemHash). HOST 2017: 51-55 - [c13]Rotem Ben Hur, Nimrod Wald, Nishil Talati, Shahar Kvatinsky:
Simple magic: Synthesis and in-memory Mapping of logic execution for memristor-aided logic. ICCAD 2017: 225-232 - [c12]Nishil Talati, Zhiying Wang
, Shahar Kvatinsky:
Rate-compatible and high-throughput architecture designs for encoding LDPC codes. ISCAS 2017: 1-4 - [c11]Nicolás Wainstein, Shahar Kvatinsky:
An RF memristor model and memristive single-pole double-throw switches. ISCAS 2017: 1-4 - [c10]John Reuben
, Rotem Ben Hur, Nimrod Wald, Nishil Talati, Ameer Haj Ali, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky:
Memristive logic: A framework for evaluation and comparison. PATMOS 2017: 1-8 - 2016
- [j11]Amir Morad, Leonid Yavits, Shahar Kvatinsky, Ran Ginosar:
Resistive GP-SIMD Processing-In-Memory. ACM Trans. Archit. Code Optim. 12(4): 57:1-57:22 (2016) - [j10]Yuval Cassuto
, Shahar Kvatinsky, Eitan Yaakobi:
Information-Theoretic Sneak-Path Mitigation in Memristor Crossbar Arrays. IEEE Trans. Inf. Theory 62(9): 4801-4813 (2016) - [c9]Eyal Rosenthal, Sergey Greshnikov, Daniel Soudry, Shahar Kvatinsky:
A fully analog memristor-based neural network with online gradient training. ISCAS 2016: 1394-1397 - [c8]Yuval Cassuto, Shahar Kvatinsky, Eitan Yaakobi:
Write sneak-path constraints avoiding disturbs in memristor crossbar arrays. ISIT 2016: 950-954 - [c7]Heonjae Ha, Ardavan Pedram, Stephen Richardson, Shahar Kvatinsky, Mark Horowitz:
Improving energy efficiency of DRAM by exploiting half page row access. MICRO 2016: 27:1-27:12 - [c6]Artem Vasilyev, Nikhil Bhagdikar, Ardavan Pedram, Stephen Richardson, Shahar Kvatinsky, Mark Horowitz:
Evaluating programmable architectures for imaging and vision applications. MICRO 2016: 52:1-52:13 - [c5]Rotem Ben Hur, Shahar Kvatinsky:
Memory Processing Unit for in-memory processing. NANOARCH 2016: 171-172 - [c4]Elad Amrani, Avishay Drori, Shahar Kvatinsky:
Logic design with unipolar memristors. VLSI-SoC 2016: 1-5 - [c3]Nimrod Wald, Elad Amrani, Avishay Drori, Shahar Kvatinsky:
Logic with Unipolar Memristors - Circuits and Design Methodology. VLSI-SoC (Selected Papers) 2016: 24-40 - [i2]Ardavan Pedram, Stephen Richardson, Sameh Galal, Shahar Kvatinsky, Mark Horowitz:
Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era. CoRR abs/1602.04183 (2016) - [i1]Xuan Yang, Jing Pu, Blaine Burton Rister, Nikhil Bhagdikar, Stephen Richardson, Shahar Kvatinsky, Jonathan Ragan-Kelley, Ardavan Pedram, Mark Horowitz:
A Systematic Approach to Blocking Convolutional Neural Networks. CoRR abs/1606.04209 (2016) - 2015
- [j9]Leonid Yavits, Shahar Kvatinsky, Amir Morad, Ran Ginosar:
Resistive Associative Processor. IEEE Comput. Archit. Lett. 14(2): 148-151 (2015) - [j8]Shahar Kvatinsky, Misbah Ramadan, Eby G. Friedman, Avinoam Kolodny:
VTEAM: A General Model for Voltage-Controlled Memristors. IEEE Trans. Circuits Syst. II Express Briefs 62-II(8): 786-790 (2015) - [j7]Daniel Soudry, Dotan Di Castro, Asaf Gal
, Avinoam Kolodny, Shahar Kvatinsky:
Memristor-Based Multilayer Neural Networks With Online Gradient Descent Training. IEEE Trans. Neural Networks Learn. Syst. 26(10): 2408-2421 (2015) - [j6]Ravi Patel, Shahar Kvatinsky, Eby G. Friedman, Avinoam Kolodny:
Multistate Register Based on Resistive RAM. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1750-1759 (2015) - 2014
- [j5]Shahar Kvatinsky, Yuval H. Nacson, Yoav Etsion, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser:
Memristor-Based Multithreading. IEEE Comput. Archit. Lett. 13(1): 41-44 (2014) - [j4]Yifat Levy, Jehoshua Bruck
, Yuval Cassuto, Eby G. Friedman, Avinoam Kolodny, Eitan Yaakobi
, Shahar Kvatinsky:
Logic operations in memory using a memristive Akers array. Microelectron. J. 45(11): 1429-1437 (2014) - [j3]Shahar Kvatinsky, Dmitry Belousov, Slavik Liman, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser:
MAGIC - Memristor-Aided Logic. IEEE Trans. Circuits Syst. II Express Briefs 61-II(11): 895-899 (2014) - [j2]Shahar Kvatinsky, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser:
Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2054-2066 (2014) - 2013
- [j1]Shahar Kvatinsky, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser:
TEAM: ThrEshold Adaptive Memristor Model. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(1): 211-221 (2013) - [c2]Yuval Cassuto, Shahar Kvatinsky, Eitan Yaakobi:
Sneak-path constraints in memristor crossbar arrays. ISIT 2013: 156-160 - 2011
- [c1]Shahar Kvatinsky, Avinoam Kolodny, Uri C. Weiser, Eby G. Friedman:
Memristor-based IMPLY logic design procedure. ICCD 2011: 142-147
Coauthor Index
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