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Hans-Jörg Pfleiderer
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- affiliation: University of Ulm, Germany
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2000 – 2009
- 2009
- [c29]Christiane Beuschel, Hans-Jörg Pfleiderer:
Fully programmable layered LDPC decoder architecture. EUSIPCO 2009: 1156-1160 - [c28]Hans-Jörg Pfleiderer, Stefan Lachowicz:
Numerically controlled oscillators using linear approximation. FPL 2009: 695-698 - 2008
- [c27]Stefan Lachowicz, Hans-Jörg Pfleiderer:
Fast Evaluation of the Square Root and Other Nonlinear Functions in FPGA. DELTA 2008: 474-477 - [c26]Oliver A. Pfänder, Reinhard Nopper, Hans-Jörg Pfleiderer, Shun Zhou, Amine Bermak:
Configurable Blocks for Multi-precision Multiplication. DELTA 2008: 478-481 - [c25]Christiane Beuschel, Hans-Jörg Pfleiderer:
FPGA implementation of a flexible decoder for long LDPC codes. FPL 2008: 185-190 - [c24]Oliver A. Pfänder, Hans-Jörg Pfleiderer:
EMMA - A suggestion for an embedded multi-precision multiplier array for FPGAs. FPL 2008: 435-438 - 2007
- [c23]Shun Zhou, Oliver A. Pfänder, Hans-Jörg Pfleiderer, Amine Bermak:
A VLSI architecture for a Run-time Multi-precision Reconfigurable Booth Multiplier. ICECS 2007: 975-978 - [c22]Christophe Layer, Daniel Schaupp, Hans-Jörg Pfleiderer:
Area and Throughput Aware Comparator Networks Optimization for Parallel Data Processing on FPGA. ISCAS 2007: 405-408 - [e1]Ricardo Augusto da Luz Reis, Adam Osseiran, Hans-Jörg Pfleiderer:
VLSI-SoC: From Systems To Silicon, Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia. IFIP 240, Springer 2007, ISBN 978-0-387-73660-0 [contents] - 2006
- [j10]Markus Buck, Tim Haulick, Hans-Jörg Pfleiderer:
Self-calibrating microphone arrays for speech signal acquisition: A systematic approach. Signal Process. 86(6): 1230-1238 (2006) - [c21]Francisco-Javier Veredas, Michael Scheppler, Hans-Jörg Pfleiderer:
Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time. DATE Designers' Forum 2006: 36-41 - [c20]Francisco-Javier Veredas, Hans-Jörg Pfleiderer:
Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs. FPL 2006: 1-2 - [c19]Francisco-Javier Veredas, Hans-Jörg Pfleiderer:
Power estimation of a LUT-based MPGA. FPT 2006: 313-316 - [c18]Francisco-Javier Veredas, Michael Scheppler, Bumei Zhai, Hans-Jörg Pfleiderer:
LUT-based MPGAs for fast turnaround time conversion flow. ISCAS 2006 - [c17]Francisco-Javier Veredas, Michael Scheppler, Bumei Zhai, Hans-Jörg Pfleiderer:
Regular Routing Architecture for a LUT-based MPGA. ISVLSI 2006: 257-262 - [c16]Jürgen Rauscher, Hans-Jörg Pfleiderer:
Sensitivity of a Power Supply Damping Method to Resistance and Current Waveform Variations. PATMOS 2006: 496-503 - 2005
- [j9]Peter Benkart, Alexander Kaiser, Andreas Munding, Markus Bschorr, Hans-Jörg Pfleiderer, Erhard Kohn, Arne Heittmann, Holger Huebner, Ulrich Ramacher:
3D Chip Stack Technology Using Through-Chip Interconnects. IEEE Des. Test Comput. 22(6): 512-518 (2005) - [j8]Cristina Tarín, Edgar Teufel, Jesús Picó, Jorge Bondia, Hans-Jörg Pfleiderer:
Comprehensive pharmacokinetic model of insulin Glargine and other insulin formulations. IEEE Trans. Biomed. Eng. 52(12): 1994-2005 (2005) - [c15]Christophe Layer, Hans-Jörg Pfleiderer:
Efficient Hardware Search Engine for Associative Content Retrieval of Long Queries in Huge Multimedia Databases. ICME 2005: 1034-1037 - [c14]Oliver A. Pfänder, Christophe Layer, Wolfgang Schlecker, Hans-Jörg Pfleiderer:
An Interactive Systemc Course Featuring Real-Time Online Compiling and Analysis. EDUTECH 2005: 121-131 - [c13]Christophe Layer, Hans-Jörg Pfleiderer:
Vertical Sorting Techniques Accelerating Associative Accesses based Information Retrieval Systems. Parallel and Distributed Computing and Networks 2005: 411-416 - 2004
- [c12]Christophe Layer, Hans-Jörg Pfleiderer:
High Performance Associative Coprocessor Architecture for Advanced Database Searching. Databases and Applications 2004: 87-92 - [c11]Christophe Layer, Hans-Jörg Pfleiderer:
A Reconfigurable Recurrent Bitonic Sorting Network for Concurrently Accessible Data. FPL 2004: 648-657 - [c10]Oliver A. Pfänder, Roland Hacker, Hans-Jörg Pfleiderer:
A Multiplexer-Based Concept for Reconfigurable Multiplier Arrays. FPL 2004: 938-942 - [c9]Christophe Layer, Hans-Jörg Pfleiderer, Christoph Heer:
A scalable compact architecture for the computation of integer binary logarithms through linear approximation. ISCAS (2) 2004: 421-424 - [c8]Markus Tahedl, Hans-Jörg Pfleiderer:
Dynamic Wire Delay and Slew Metrics for Integrated Bus Structures. PATMOS 2004: 69-78 - 2003
- [c7]Markus Tahedl, Hans-Jörg Pfleiderer:
A driver load model for capacitive coupled on-chip interconnect buses. SoC 2003: 101-104 - [c6]Edgar Teufel, Marco Kletting, Werner G. Teich, Hans-Jörg Pfleiderer, C. Tarin-Sauer:
Modelling the glucose metabolism with backpropagation through time trained Elman nets. NNSP 2003: 789-798 - 2002
- [j7]Slavek Bulach, Anton Brauchle, Hans-Jörg Pfleiderer, Zdenek Kucerovsky:
Design and Implementation of Discrete Event Control Systems: A Petri Net Based Hardware Approach. Discret. Event Dyn. Syst. 12(3): 287-309 (2002) - [c5]Wolfgang Schlecker, Achim Engelhart, Werner G. Teich, Hans-Jörg Pfleiderer:
Hardware Implementation of a Multiuser Detection Scheme Based on Recurrent Neural Networks. FPL 2002: 1097-1100 - 2001
- [c4]Slavek Bulach, Anton Brauchle, Hans-Jörg Pfleiderer, Zdenek Kucerovsky:
Petri Net Based Design and Implementation Methodology for Discrete Event Control Systems. ICATPN 2001: 81-100
1990 – 1999
- 1999
- [c3]Stefan Lachowicz, Kamran Eshraghian, Hans-Jörg Pfleiderer:
Self-Timed Techniques for Low-Power Digital Arithmetic in GaAs VLSI. VLSI 1999: 245-256 - [c2]Stefan Lachowicz, Kamran Eshraghian, M. Hollreiser, Hans-Jörg Pfleiderer:
Self-timed MESFET gallium arsenide circuit techniques for a direct digital frequency synthesiser. ISSPA 1999: 575-578 - 1996
- [j6]Gerhard Nebel, Ulrich Kleine, Hans-Jörg Pfleiderer:
Large bandwidth BiCMOS operational amplifiers for SC video applications. IEEE J. Solid State Circuits 31(6): 828-834 (1996) - 1995
- [j5]Gerhard Nebel, Ulrich Kleine, Hans-Jörg Pfleiderer:
Symbolic pole/zero calculation using SANTAFE. IEEE J. Solid State Circuits 30(7): 752-761 (1995) - [j4]Martin Rau, Hans-Jörg Pfleiderer:
An ECL to CMOS level converter with complementary bipolar output stage. IEEE J. Solid State Circuits 30(7): 781-787 (1995) - 1994
- [c1]Gerhard Nebel, Ulrich Kleine, Hans-Jörg Pfleiderer:
Large Bandwidth BiCMOS Operational Amplifiers for SC-Video-Applications. ISCAS 1994: 85-88
1980 – 1989
- 1985
- [j3]Egon Hörbst, H. Oechslein, Hans-Jörg Pfleiderer:
VLSI - Auswirkungen auf konventionelle Rechnerstrukturen. Inform. Spektrum 8(1): 7-19 (1985) - 1983
- [j2]G. Grassl, Hans-Jörg Pfleiderer:
A function-independent self-test for large programmable logic arrays. Integr. 1(1): 71-80 (1983)
1970 – 1979
- 1979
- [j1]Hans-Jörg Pfleiderer, Karl Knauer:
Antialiasing Filter with an Improved S/N Ratio. IEEE Trans. Commun. 27(2): 430-431 (1979)
Coauthor Index
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