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2010 – 2019
- 2013
[j7]Graham M. Megson, José O. Cadenas, Robert Simon Sherratt
, Pablo Huerta, Wen-Chung Kao:
A Parallel Quantum Histogram Architecture. IEEE Trans. Circuits Syst. II Express Briefs 60-II(7): 437-441 (2013)- [j6]José O. Cadenas, Robert Simon Sherratt, Pablo Huerta, Wen-Chung Kao, Graham M. Megson:
C-slow retimed parallel histogram architectures for consumer imaging devices. IEEE Trans. Consumer Electron. 59(2) (2013) - [c11]José O. Cadenas, R. Simon Sherratt, Pablo Huerta, Wen-Chung Kao, Graham M. Megson:
Parallel pipelined histogram architecture via C-slow retiming. ICCE 2013: 230-231 - 2011
- [j5]José O. Cadenas, Robert Simon Sherratt, Pablo Huerta, Wen-Chung Kao:
Parallel pipelined array architectures for real-time histogram computation in consumer devices. IEEE Trans. Consumer Electron. 57(4): 1460-1464 (2011) - [j4]César Pedraza, Javier Castillo, José Ignacio Martínez, Pablo Huerta, José Luis Bosque, Javier Cano:
Genetic Algorithm for Boolean minimization in an FPGA cluster. J. Supercomput. 58(2): 244-252 (2011) - [c10]Emilio Castillo, Javier Castillo, Javier Cano, Pablo Huerta, José Ignacio Martínez:
A Key Size Configurable High Speed RSA Coprocessor. FCCM 2011: 250 - 2010
- [j3]César Pedraza, Emilio Castillo, Javier Castillo, José Luis Bosque, José Ignacio Martínez, Oscar David Robles, Javier Cano, Pablo Huerta:
Content-based image retrieval algorithm acceleration in a low-cost reconfigurable FPGA cluster. J. Syst. Archit. 56(11): 633-640 (2010) - [c9]Otto Esko, Pekka Jääskeläinen, Pablo Huerta, Carlos S. de La Lama, Jarmo Takala, José Ignacio Martínez:
Customized Exposed Datapath Soft-Core Design Flow with Compiler Support. FPL 2010: 217-222 - [c8]Pekka Jääskeläinen, Carlos S. de La Lama, Pablo Huerta, Jarmo Takala:
OpenCL-based design methodology for application-specific processors. ICSAMOS 2010: 223-230
2000 – 2009
- 2009
- [c7]Javier Castillo, José Luis Bosque, Emilio Castillo, Pablo Huerta, José Ignacio Martínez:
Hardware accelerated montecarlo financial simulation over low cost FPGA cluster. IPDPS 2009: 1-8 - [c6]César Pedraza, Javier Castillo, José Ignacio Martínez, Pablo Huerta, José Luis Bosque, Javier Cano:
Speeding up combinational synthesis in an FPGA cluster. PARCO 2009: 600-607 - [c5]Pablo Huerta, Javier Castillo, César Pedraza, Javier Cano, José Ignacio Martínez:
Symmetric Multiprocessor Systems on FPGA. ReConFig 2009: 279-283 - 2008
- [j2]César Pedraza, Javier Castillo, José Ignacio Martínez, Pablo Huerta, Carlos S. de La Lama:
Self-reconfigurable secure file system for embedded Linux. IET Comput. Digit. Tech. 2(6): 461-470 (2008) - [c4]Pablo Huerta, Javier Castillo, Carlos Sanchez, José Ignacio Martínez:
Operating System for Symmetric Multiprocessors on FPGA. ReConFig 2008: 157-162 - 2007
- [j1]Javier Castillo, Pablo Huerta, José Ignacio Martínez:
Secure IP downloading for SRAM FPGAs. Microprocess. Microsystems 31(2): 77-86 (2007) - 2006
- [c3]Javier Castillo, Pablo Huerta, César Pedraza, José Ignacio Martínez:
A Self-Reconfigurable Multimedia Player on FPGA. ReConFig 2006: 6-11 - 2005
- [c2]Javier Castillo, Pablo Huerta, Víctor López, José Ignacio Martínez:
A secure self-reconfiguring architecture based on open-source hardware. ReConFig 2005 - 2004
- [c1]María del Milagro Bolado, Hector Posadas, Javier Castillo, Pablo Huerta, Pablo Sánchez, Carlos Sánchez, Häkan Fouren, Francisco Blasco:
Platform Based on Open-Source Cores for Industrial Applications. DATE 2004: 1014-1019
Coauthor Index
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