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Kyung Whan Kim
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2010 – 2019
- 2019
- [c7]Dongkyun Kim, Minsu Park, Sungchun Jang, Jun-Yong Song, Hankyu Chi, Geunho Choi, Sunmyung Choi, Jaeil Kim, Changhyun Kim, Kyung Whan Kim, Kibong Koo, Seonghwi Song, Yongmi Kim, Dong-Uk Lee, Jaejin Lee, Dae Suk Kim, Ki Hun Kwon, Minsik Han, Byeongchan Choi, Hongjung Kim, Sanghyun Ku, Yeonuk Kim, Jong-Sam Kim, Sanghui Kim, Youngsuk Seo, Seungwook Oh, Dain Im, Haksong Kim, Jonghyuck Choi, Jinil Chung, Changhyun Lee, Yongsung Lee, Joo-Hwan Cho, Junhyun Chun, Jonghoon Oh:
A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme. ISSCC 2019: 380-382 - 2016
- [c6]Jong-Chern Lee, Jihwan Kim, Kyung Whan Kim, Young Jun Ku, Dae Suk Kim, Chunseok Jeong, Tae Sik Yun, Hongjung Kim, Ho Sung Cho, Sangmuk Oh, Hyun Sung Lee, Ki Hun Kwon, Dong Beom Lee, Young Jae Choi, Jaejin Lee, Hyeon Gon Kim, Jun Hyun Chun, Jonghoon Oh, Seok Hee Lee:
High bandwidth memory(HBM) with TSV technique. ISOCC 2016: 181-182 - [c5]Jong-Chern Lee, Jihwan Kim, Kyung Whan Kim, Young Jun Ku, Dae Suk Kim, Chunseok Jeong, Tae Sik Yun, Hongjung Kim, Ho Sung Cho, Yeon Ok Kim, Jae-Hwan Kim, Jin Ho Kim, Sangmuk Oh, Hyun Sung Lee, Ki Hun Kwon, Dong Beom Lee, Young Jae Choi, Jeajin Lee, Hyeon Gon Kim, Jun Hyun Chun, Jonghoon Oh, Seok Hee Lee:
18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface. ISSCC 2016: 318-319 - 2015
- [j2]Dong-Uk Lee, Kyung Whan Kim, Kwan-Weon Kim, Kang Seol Lee, Sang Jin Byeon, Jae-Hwan Kim, Jin-Hee Cho, Jaejin Lee, Jun Hyun Chun:
A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits. IEEE J. Solid State Circuits 50(1): 191-203 (2015) - [c4]Dong-Uk Lee, Kang Seol Lee, Yongwoo Lee, Kyung Whan Kim, Jong-Ho Kang, Jaejin Lee, Jun Hyun Chun:
Design considerations of HBM stacked DRAM and the memory architecture extension. CICC 2015: 1-8 - 2014
- [c3]Dong-Uk Lee, Kyung Whan Kim, Kwan-Weon Kim, Hongjung Kim, Ju Young Kim, Young Jun Park, Jae Hwan Kim, Dae Suk Kim, Heat Bit Park, Jin Wook Shin, Jang Hwan Cho, Ki Hun Kwon, Min Jeong Kim, Jaejin Lee, Kunwoo Park, Byong-Tae Chung, Sung-Joo Hong:
25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV. ISSCC 2014: 432-433 - [c2]Dong-Uk Lee, Kyung Whan Kim, Kwan-Weon Kim, Kang Seol Lee, Sang Jin Byeon, Jin-Hee Cho, Han Ho Jin, Sang Kyun Nam, Jaejin Lee, Jun Hyun Chun, Sung-Joo Hong:
An exact measurement and repair circuit of TSV connections for 128GB/s high-bandwidth memory(HBM) stacked DRAM. VLSIC 2014: 1-2 - 2012
- [j1]Hyun-Woo Lee, Hoon Choi, Beom-Ju Shin, Kyung-Hoon Kim, Kyung Whan Kim, Jaeil Kim, Kwang Hyun Kim, Jongho Jung, Jae-Hwan Kim, Eun Young Park, Jong-Sam Kim, Jong-Hwan Kim, Jin-Hee Cho, Nam Gyu Rye, Jun Hyun Chun, Yunsaing Kim, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung:
A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces. IEEE J. Solid State Circuits 47(6): 1436-1447 (2012) - 2010
- [c1]Hyun-Woo Lee, Yong-Hoon Kim, Won-Joo Yun, Eun Young Park, Kang Youl Lee, Jaeil Kim, Kwang Hyun Kim, Jongho Jung, Kyung Whan Kim, Nam Gyu Rye, Kwan-Weon Kim, Jun Hyun Chun, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung, Joong Sik Kih:
A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface. ISCAS 2010: 3861-3864
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