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Masaya Sumita
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2010 – 2019
- 2013
- [c7]Wim Dehaene, Masaya Sumita:
Session 24 overview: Energy-aware digital design. ISSCC 2013: 418-419 - 2012
- [c6]Michael Phan, Masaya Sumita:
Session 28 overview: Adaptive and low-power circuits: Energy-efficient digital subcommittee. ISSCC 2012: 476-477 - 2011
- [c5]Tobias Noll, Raney Southerland, Vladimir Stojanovic, Sonia Leon, Lew Chua-Eoan, Alice Wang, Byeong-Gyu Nam, Masaya Sumita:
Design of "green" high-performance processor circuits. ISSCC 2011: 518-519
2000 – 2009
- 2007
- [c4]Masaitsu Nakajima, Takao Yamamoto, Masayuki Yamasaki, Tetsu Hosoki, Masaya Sumita:
Low Power Techniques for Mobile Application SoCs Based on Integrated Platform "UniPhier". ASP-DAC 2007: 649-653 - 2006
- [j2]Yuuichirou Ikeda, Masaya Sumita, Makoto Nagata:
Multi-Ported Register File for Reducing the Impact of PVT Variation. IEICE Trans. Electron. 89-C(3): 356-363 (2006) - [c3]Masaya Sumita, T. Wada:
A 14: 1 dynamic MUX FF with select activity detection. ISSCC 2006: 1775-1784 - 2005
- [j1]Masaya Sumita, Shiro Sakiyama, Masayoshi Kinoshita, Yuta Araki, Yuichiro Ikeda, Kohei Fukuoka:
Mixed body bias techniques with fixed Vt and Ids generation circuits. IEEE J. Solid State Circuits 40(1): 60-66 (2005) - [c2]Masaya Sumita:
High resolution body bias techniques for reducing the impacts of leakage current and parasitic bipolar. ISLPED 2005: 203-208 - 2004
- [c1]Shen Lin, Makoto Nagata, Kenji Shimazaki, Kazuhiro Satoh, Masaya Sumita, Hiroyuki Tsujikawa, Andrew T. Yang:
Full-chip vectorless dynamic power integrity analysis and verification against 100uV/100ps-resolution measurement. CICC 2004: 509-512
Coauthor Index
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