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2020 – today
- 2020
[j120]Qin Li, Yuze Yang, Tianxiang Lan, Huifeng Zhu, Qi Wei, Fei Qiao
, Xinjun Liu, Huazhong Yang:
MSP-MFCC: Energy-Efficient MFCC Feature Extraction Method With Mixed-Signal Processing Architecture for Wearable Speech Recognition Applications. IEEE Access 8: 48720-48730 (2020)- [j119]Xuefei Ning, Yin Zheng, Zhuxi Jiang, Yu Wang, Huazhong Yang, Junzhou Huang, Peilin Zhao:
Nonparametric Topic Modeling with Neural Inference. Neurocomputing 399: 296-306 (2020) - [j118]Zhe Yuan, Yongpan Liu, Jinshan Yue, Yixiong Yang, Jingyu Wang, Xiaoyu Feng, Jian Zhao, Xueqing Li, Huazhong Yang:
STICKER: An Energy-Efficient Multi-Sparsity Compatible Accelerator for Convolutional Neural Networks in 65-nm CMOS. IEEE J. Solid State Circuits 55(2): 465-477 (2020) - [j117]Yuxuan Huang, Jian Zhao, Wenyu Sun, Huazhong Yang, Yongpan Liu:
Investigation and Modeling of Multi-Node Body Channel Wireless Power Transfer. Sensors 20(1): 156 (2020) - [j116]Bo Zhao, Jingna Mao, Jian Zhao, Huazhong Yang, Yong Lian:
The Role and Challenges of Body Channel Communication in Wearable Flexible Electronics. IEEE Trans. Biomed. Circuits Syst. 14(2): 283-296 (2020) - [j115]Yi Cai, Xiaoming Chen, Lu Tian, Yu Wang, Huazhong Yang:
Enabling Secure NVM-Based in-Memory Neural Network Computing by Sparse Fast Gradient Encryption. IEEE Trans. Computers 69(11): 1596-1610 (2020) - [j114]Yi Cai, Tianqi Tang, Lixue Xia, Boxun Li, Yu Wang, Huazhong Yang:
Low Bit-Width Convolutional Neural Network on RRAM. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(7): 1414-1427 (2020) - [j113]Zhe Chen, Xinjun Liu, Huazhong Yang, Huifeng Zhu, Erxiang Ren, Zheyu Liu, Kaige Jia, Li Luo, Xuan Zhang, Qi Wei, Fei Qiao:
Processing Near Sensor Architecture in Mixed-Signal Domain With CMOS Image Sensor of Convolutional-Kernel-Readout Method. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(2): 389-400 (2020) - [j112]Zheyu Liu, Erxiang Ren, Fei Qiao, Qi Wei, Xinjun Liu, Li Luo, Huichan Zhao, Huazhong Yang:
NS-CIM: A Current-Mode Computation-in-Memory Architecture Enabling Near-Sensor Processing for Intelligent IoT Vision Nodes. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(9): 2909-2922 (2020) - [j111]Zichen Fan, Zheyu Liu, Zheng Qu, Fei Qiao, Qi Wei, Xinjun Liu, Yinan Sun, Shuzheng Xu, Huazhong Yang:
ASP-SIFT: Using Analog Signal Processing Architecture to Accelerate Keypoint Detection of SIFT Algorithm. IEEE Trans. Very Large Scale Integr. Syst. 28(1): 198-211 (2020) - [c267]Wenshuo Li, Guangjun Ge, Kaiyuan Guo, Xiaoming Chen, Qi Wei, Zhen Gao, Yu Wang, Huazhong Yang:
Soft Error Mitigation for Deep Convolution Neural Network on FPGA Accelerators. AICAS 2020: 1-5 - [c266]Wenshuo Li, Xuefei Ning, Guangjun Ge, Xiaoming Chen, Yu Wang, Huazhong Yang:
FTT-NAS: Discovering Fault-Tolerant Neural Architecture. ASP-DAC 2020: 211-216 - [c265]Hanbo Sun, Zhenhua Zhu, Yi Cai, Xiaoming Chen, Yu Wang, Huazhong Yang:
An Energy-Efficient Quantized and Regularized Training Framework For Processing-In-Memory Accelerators. ASP-DAC 2020: 325-330 - [c264]Juejian Wu, Yixin Xu, Bowen Xue, Yu Wang, Yongpan Liu, Huazhong Yang, Xueqing Li:
Adaptive Circuit Approaches to Low-Power Multi-Level/Cell FeFET Memory. ASP-DAC 2020: 407-413 - [c263]Shulin Zeng, Hanbo Sun, Yu Xing, Xuefei Ning, Yi Shan, Xiaoming Chen, Yu Wang, Huazhong Yang:
Black Box Search Space Profiling for Accelerator-Aware Neural Architecture Search. ASP-DAC 2020: 518-523 - [c262]Jingyu Wang, Songming Yu, Jinshan Yue, Zhe Yuan, Zhuqing Yuan, Huazhong Yang, Xueqing Li, Yongpan Liu:
High PE Utilization CNN Accelerator with Channel Fusion Supporting Pattern-Compressed Sparse Neural Networks. DAC 2020: 1-6 - [c261]Han Xu, Maimaiti Nazhamaiti, Yidong Liu, Fei Qiao, Qi Wei, Xinjun Liu, Huazhong Yang:
Utilizing Direct Photocurrent Computation and 2D Kernel Scheduling to Improve In-Sensor-Processing Efficiency. DAC 2020: 1-6 - [c260]Jincheng Yu, Zhilin Xu, Shulin Zeng, Chao Yu, Jiantao Qiu, Chaoyang Shen, Yuanfan Xu, Guohao Dai, Yu Wang, Huazhong Yang:
INCA: INterruptible CNN Accelerator for Multi-tasking in Embedded Robots. DAC 2020: 1-6 - [c259]Hongtao Zhong, Mingyang Gu, Juejian Wu, Huazhong Yang, Xueqing Li:
Design of Almost-Nonvolatile Embedded DRAM Using Nanoelectromechanical Relay Devices. DATE 2020: 1223-1228 - [c258]Wenyu Sun, Chen Tang, Weigui Li, Zhuqing Yuan, Huazhong Yang, Yongpan Liu:
High-Quality Single-Model Deep Video Compression with Frame-Conv3D and Multi-frame Differential Modulation. ECCV (30) 2020: 239-254 - [c257]Ming Chen, Guijin Wang, Zijian Ding, Jiawei Li, Huazhong Yang:
Unsupervised Domain Adaptation for ECG Arrhythmia Classification. EMBC 2020: 304-307 - [c256]Zhilin Xu, Jincheng Yu, Chao Yu, Hao Shen, Yu Wang, Huazhong Yang:
CNN-based Feature-point Extraction for Real-time Visual SLAM on Embedded FPGA. FCCM 2020: 33-37 - [c255]Shulin Zeng, Guohao Dai, Hanbo Sun, Kai Zhong, Guangjun Ge, Kaiyuan Guo, Yu Wang, Huazhong Yang:
Enabling Efficient and Flexible FPGA Virtualization for Deep Learning in the Cloud. FCCM 2020: 102-110 - [c254]Jincheng Yu, Zhilin Xu, Shulin Zeng, Chao Yu, Jiantao Qiu, Chaoyang Shen, Yuanfan Xu, Guohao Dai, Yu Wang, Huazhong Yang:
INCAME: INterruptible CNN Accelerator for Multi-robot Exploration. FPGA 2020: 316 - [c253]Shulin Zeng, Guohao Dai, Kai Zhong, Hanbo Sun, Guangjun Ge, Kaiyuan Guo, Yu Wang, Huazhong Yang:
Enable Efficient and Flexible FPGA Virtualization for Deep Learning in the Cloud. FPGA 2020: 317 - [c252]Zhenhua Zhu, Hanbo Sun, Kaizhong Qiu, Lixue Xia, Gokul Krishnan, Guohao Dai, Dimin Niu, Xiaoming Chen, Xiaobo Sharon Hu, Yu Cao, Yuan Xie, Yu Wang, Huazhong Yang:
MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems. ACM Great Lakes Symposium on VLSI 2020: 83-88 - [c251]Jincheng Yu, Feng Gao, Jianfei Cao, Chao Yu, Zhaoliang Zhang, Zhengfeng Huang, Yu Wang, Huazhong Yang:
CNN-based Monocular Decentralized SLAM on embedded FPGA. IPDPS Workshops 2020: 66-73 - [c250]Qin Li, Sheng Lin, Changlu Liu, Yidong Liu, Fei Qiao, Yanzhi Wang, Huazhong Yang:
NS-KWS: joint optimization of near-sensor processing architecture and low-precision GRU for always-on keyword spotting. ISLPED 2020: 97-102 - [c249]Yixiong Yang, Zhe Yuan, Fang Su, Fanyang Cheng, Zhuqing Yuan, Huazhong Yang, Yongpan Liu:
Multi-channel precision-sparsity-adapted inter-frame differential data codec for video neural network processor. ISLPED 2020: 103-108 - [c248]Mingyen Lee, Wenjun Tang, Bowen Xue, Juejian Wu, Mingyuan Ma, Yu Wang, Yongpan Liu, Deliang Fan, Vijaykrishnan Narayanan, Huazhong Yang, Xueqing Li:
FeFET-based low-power bitwise logic-in-memory with direct write-back and data-adaptive dynamic sensing interface. ISLPED 2020: 127-132 - [c247]Han Xu, Ziru Li, Fei Qiao, Qi Wei, Xinjun Liu, Huazhong Yang:
CDS-RSRAM: a Reconfigurable SRAM Architecture to Reduce Read Power with Column Data Segmentation. ISQED 2020: 52-59 - [c246]Shujuan Yin, Zheyu Liu, Guihong Li, Fei Qiao, Qi Wei, Yuanfeng Wu, Lianru Gao, Xinjun Liu, Huazhong Yang:
RARA: Dataflow Based Error Compensation Methods with Runtime Accuracy-Reconfigurable Adder. ISQED 2020: 60-66 - [c245]Zhe Yuan, Yixiong Yang, Jinshan Yue, Ruoyang Liu, Xiaoyu Feng, Zhiting Lin, Xiulong Wu, Xueqing Li, Huazhong Yang, Yongpan Liu:
14.2 A 65nm 24.7µJ/Frame 12.3mW Activation-Similarity-Aware Convolutional Neural Network Video Processor Using Hybrid Precision, Inter-Frame Data Reuse and Mixed-Bit-Width Difference-Frame Data Codec. ISSCC 2020: 232-234 - [c244]Jinshan Yue, Zhe Yuan, Xiaoyu Feng, Yifan He, Zhixiao Zhang, Xin Si, Ruhui Liu, Meng-Fan Chang, Xueqing Li, Huazhong Yang, Yongpan Liu:
14.3 A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse. ISSCC 2020: 234-236 - [c243]Yanming Zhang, Xu Qiu, Qin Li, Fei Qiao, Qi Wei, Li Luo, Huazhong Yang:
Optimization and Evaluation of Energy-Efficient Mixed-Signal MFCC Feature Extraction Architecture. ISVLSI 2020: 506-511 - [i32]Xuefei Ning, Guangjun Ge, Wenshuo Li, Zhenhua Zhu, Yin Zheng, Xiaoming Chen, Zhen Gao, Yu Wang, Huazhong Yang:
FTT-NAS: Discovering Fault-Tolerant Neural Architecture. CoRR abs/2003.10375 (2020) - [i31]Shulin Zeng, Guohao Dai, Hanbo Sun, Kai Zhong, Guangjun Ge, Kaiyuan Guo, Yu Wang, Huazhong Yang:
Enabling Efficient and Flexible FPGA Virtualization for Deep Learning in the Cloud. CoRR abs/2003.12101 (2020) - [i30]Xuefei Ning, Yin Zheng, Tianchen Zhao, Yu Wang, Huazhong Yang:
A Generic Graph-based Neural Architecture Encoding Scheme for Predictor-based NAS. CoRR abs/2004.01899 (2020) - [i29]Xuefei Ning, Tianchen Zhao, Wenshuo Li, Peng Lei, Yu Wang, Huazhong Yang:
DSA: More Efficient Budgeted Pruning via Differentiable Sparsity Allocation. CoRR abs/2004.02164 (2020) - [i28]Kai Zhong, Tianchen Zhao, Xuefei Ning, Shulin Zeng, Kaiyuan Guo, Yu Wang, Huazhong Yang:
Towards Lower Bit Multiplication for Convolutional Neural Network Training. CoRR abs/2006.02804 (2020) - [i27]Guyue Huang, Guohao Dai, Yu Wang, Huazhong Yang:
GE-SpMM: General-purpose Sparse Matrix-Matrix Multiplication on GPUs for Graph Neural Networks. CoRR abs/2007.03179 (2020) - [i26]Tong Wu, Xuefei Ning, Wenshuo Li, Ranran Huang, Huazhong Yang, Yu Wang:
Physical Adversarial Attack on Vehicle Detector in the Carla Simulator. CoRR abs/2007.16118 (2020) - [i25]Xuefei Ning, Wenshuo Li, Zixuan Zhou, Tianchen Zhao, Yin Zheng, Shuang Liang, Huazhong Yang, Yu Wang:
A Surgery of the Neural Architecture Evaluators. CoRR abs/2008.03064 (2020) - [i24]Songming Yu, Yongpan Liu, Lu Zhang, Jingyu Wang, Jinshan Yue, Zhuqing Yuan, Xueqing Li, Huazhong Yang:
High Area/Energy Efficiency RRAM CNN Accelerator with Kernel-Reordering Weight Mapping Scheme Based on Pattern Pruning. CoRR abs/2010.06156 (2020)
2010 – 2019
- 2019
- [j110]Xueqing Li, Juejian Wu, Kai Ni, Sumitha George, Kaisheng Ma, John Sampson, Sumeet Kumar Gupta, Yongpan Liu, Huazhong Yang, Suman Datta, Vijaykrishnan Narayanan:
Design of 2T/Cell and 3T/Cell Nonvolatile Memories with Emerging Ferroelectric FETs. IEEE Des. Test 36(3): 39-45 (2019) - [j109]Guijin Wang, Chenshuang Zhang, Yongpan Liu, Huazhong Yang, Dapeng Fu, Haiqing Wang, Ping Zhang:
A global and updatable ECG beat classification system based on recurrent neural networks and active learning. Inf. Sci. 501: 523-542 (2019) - [j108]Yongpan Liu, Fang Su, Yixiong Yang, Zhibo Wang, Yiqun Wang, Zewei Li, Xueqing Li, Ryuji Yoshimura, Takashi Naiki, Takashi Tsuwa, Takahiko Saito, Zhongjun Wang, Koji Taniuchi, Huazhong Yang:
A 130-nm Ferroelectric Nonvolatile System-on-Chip With Direct Peripheral Restore Architecture for Transient Computing System. IEEE J. Solid State Circuits 54(3): 885-895 (2019) - [j107]Li Luo, Zhe Chen, Xinghua Yang, Fei Qiao, Qi Wei, Huazhong Yang:
A single clock cycle approximate adder with hybrid prediction and error compensation methods. Microelectron. J. 87: 45-50 (2019) - [j106]Yuhao Xiao, Guijin Wang, Xiaowei Hu, Chenbo Shi, Long Meng, Huazhong Yang:
Guided, Fusion-Based, Large Depth-of-field 3D Imaging Using a Focal Stack. Sensors 19(22): 4845 (2019) - [j105]Wenyu Sun, Jian Zhao, Yuxuan Huang, Yinan Sun, Huazhong Yang, Yongpan Liu:
Dynamic Channel Modeling and OFDM System Analysis for Capacitive Coupling Body Channel Communication. IEEE Trans. Biomed. Circuits Syst. 13(4): 735-745 (2019) - [j104]Jian Zhao, Wenyu Sun, Jingna Mao, Yuxuan Huang, Bo Zhao, Yongpan Liu, Huazhong Yang:
An Auto Loss Co Jian Zhaompensation System for Capacitive-Coupled Body Channel Communication. IEEE Trans. Biomed. Circuits Syst. 13(4): 756-765 (2019) - [j103]Guohao Dai, Tianhao Huang, Yu Wang, Huazhong Yang, John Wawrzynek:
HyVE: Hybrid Vertex-Edge Memory Hierarchy for Energy-Efficient Graph Processing. IEEE Trans. Computers 68(8): 1131-1146 (2019) - [j102]Guohao Dai, Tianhao Huang, Yuze Chi, Jishen Zhao, Guangyu Sun, Yongpan Liu, Yu Wang, Yuan Xie, Huazhong Yang:
GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(4): 640-653 (2019) - [j101]Ming Cheng, Lixue Xia, Zhenhua Zhu, Yi Cai, Yuan Xie, Yu Wang, Huazhong Yang:
TIME: A Training-in-Memory Architecture for RRAM-Based Deep Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(5): 834-847 (2019) - [j100]Qinghang Zhao, Wenyu Sun, Jiaqing Zhao, Jian Zhao, Hailong Yao, Tsung-Yi Ho, Xiaojun Guo, Huazhong Yang, Yongpan Liu:
Design Methodology for TFT-Based Pseudo-CMOS Logic Array With Multilayer Interconnection Architecture and Optimization Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(11): 2043-2057 (2019) - [j99]Longqiang Lai, Xueqing Li, Yushen Fu, Yongpan Liu, Huazhong Yang:
Demystifying and Mitigating Code-Dependent Switching Distortions in Current-Steering DACs. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(1): 68-81 (2019) - [j98]Jinshan Yue, Yongpan Liu, Zhe Yuan, Zhibo Wang, Qingwei Guo, Jinyang Li, Chengmo Yang, Huazhong Yang:
A 3.77TOPS/W Convolutional Neural Network Processor With Priority-Driven Kernel Optimization. IEEE Trans. Circuits Syst. II Express Briefs 66-II(2): 277-281 (2019) - [j97]Yixiong Yang, Xin Shi, Fang Su, Zhibo Wang, Pei Yang, Huazhong Yang, Yongpan Liu:
A 2.2-GHz Configurable Direct Digital Frequency Synthesizer Based on LUT and Rotation. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(5): 1970-1980 (2019) - [j96]Fang Su, Yongpan Liu, Xiao Sheng, Hyung Gyu Lee, Naehyuck Chang, Huazhong Yang:
A Task Failure Rate Aware Dual-Channel Solar Power System for Nonvolatile Sensor Nodes. ACM Trans. Embed. Comput. Syst. 18(4): 33:1-33:21 (2019) - [j95]Kaiyuan Guo, Shulin Zeng, Jincheng Yu, Yu Wang, Huazhong Yang:
[DL] A Survey of FPGA-based Neural Network Inference Accelerators. ACM Trans. Reconfigurable Technol. Syst. 12(1): 2:1-2:26 (2019) - [c242]Xiaoyu Feng, Jinshan Yue, Qingwei Guo, Huazhong Yang, Yongpan Liu:
Accelerating CNN-RNN Based Machine Health Monitoring on FPGA. AICAS 2019: 184-188 - [c241]Guohao Dai, Tianhao Huang, Yu Wang, Huazhong Yang, John Wawrzynek:
GraphSAR: a sparsity-aware processing-in-memory architecture for large-scale graph processing on ReRAMs. ASP-DAC 2019: 120-126 - [c240]Jinshan Yue, Yongpan Liu, Fang Su, Shuangchen Li, Zhe Yuan, Zhibo Wang, Wenyu Sun, Xueqing Li, Huazhong Yang:
AERIS: area/energy-efficient 1T2R ReRAM based processing-in-memory neural network system-on-a-chip. ASP-DAC 2019: 146-151 - [c239]Jingyu Wang, Zhe Yuan, Ruoyang Liu, Huazhong Yang, Yongpan Liu:
An N-way group association architecture and sparse data group association load balancing algorithm for sparse CNN accelerators. ASP-DAC 2019: 329-334 - [c238]Zhe Yuan, Jingyu Wang, Yixiong Yang, Jinshan Yue, Zhibo Wang, Xiaoyu Feng, Yanzhi Wang, Xueqing Li, Huazhong Yang, Yongpan Liu:
A Sparse-Adaptive CNN Processor with Area/Performance balanced N-Way Set-Associate PE Arrays Assisted by a Collision-Aware Scheduler. A-SSCC 2019: 61-64 - [c237]Jian Zhao, Jingna Mao, Wenyu Sun, Yuxuan Huang, Yixiong Yang, Huazhong Yang, Yongpan Liu:
A 4-Mbps 41-pJ/bit On-off Keying Transceiver for Body-channel Communication with Enhanced Auto Loss Compensation Technique. A-SSCC 2019: 173-176 - [c236]Zhenhua Zhu, Hanbo Sun, Yujun Lin, Guohao Dai, Lixue Xia, Song Han, Yu Wang, Huazhong Yang:
A Configurable Multi-Precision CNN Computing Framework Based on Single Bit RRAM. DAC 2019: 56 - [c235]Juejian Wu, Hongtao Zhong, Kai Ni, Yongpan Liu, Huazhong Yang, Xueqing Li:
A 3T/Cell Practical Embedded Nonvolatile Memory Supporting Symmetric Read and Write Access Based on Ferroelectric FETs. DAC 2019: 82 - [c234]Shulin Zeng, Yujun Lin, Shuang Liang, Junlong Kang, Dongliang Xie, Yi Shan, Song Han, Yu Wang, Huazhong Yang:
A Fine-Grained Sparse Accelerator for Multi-Precision DNN. FPGA 2019: 185 - [c233]Kaiyuan Guo, Shuang Liang, Jincheng Yu, Xuefei Ning, Wenshuo Li, Yu Wang, Huazhong Yang:
Compressed CNN Training with FPGA-based Accelerator. FPGA 2019: 189 - [c232]Xuedi Wang, Xueqing Li, Longqiang Lai, Huazhong Yang:
A 16b Clockless Digital-to-Analog Converter with Ultra-Low-Cost Poly Resistors Supporting Wide-Temperature Range from -40°C to 85°C. ACM Great Lakes Symposium on VLSI 2019: 267-270 - [c231]Zheyu Liu, Guihong Li, Fei Qiao, Qi Wei, Ping Jin, Xinjun Liu, Huazhong Yang:
Concrete: A Per-layer Configurable Framework for Evaluating DNN with Approximate Operators. ICASSP 2019: 1552-1556 - [c230]Yi Cai, Xiaoming Chen, Lu Tian, Yu Wang, Huazhong Yang:
Enabling Secure in-Memory Neural Network Computing by Sparse Fast Gradient Encryption. ICCAD 2019: 1-8 - [c229]Zheyu Liu, Kaige Jia, Weiqiang Liu, Qi Wei, Fei Qiao, Huazhong Yang:
INA: Incremental Network Approximation Algorithm for Limited Precision Deep Neural Networks. ICCAD 2019: 1-7 - [c228]Zhenhua Zhu, Mingyuan Ma, Jialong Liu, Liying Xu, Xiaoming Chen, Yuchao Yang, Yu Wang, Huazhong Yang:
A General Logic Synthesis Framework for Memristor-based Logic Design. ICCAD 2019: 1-8 - [c227]Jialong Liu, Mingyuan Ma, Zhenhua Zhu, Yu Wang, Huazhong Yang:
HDC-IM: Hyperdimensional Computing In-Memory Architecture based on RRAM. ICECS 2019: 450-453 - [c226]Jinshan Yue, Ruoyang Liu, Wenyu Sun, Zhe Yuan, Zhibo Wang, Yung-Ning Tu, Yi-Ju Chen, Ao Ren, Yanzhi Wang, Meng-Fan Chang, Xueqing Li, Huazhong Yang, Yongpan Liu:
A 65nm 0.39-to-140.3TOPS/W 1-to-12b Unified Neural Network Processor Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1 × Higher TOPS/mm2and 6T HBST-TRAM-Based 2D Data-Reuse Architecture. ISSCC 2019: 138-140 - [c225]Yiming Hu, Shuang Liang, Jincheng Yu, Yu Wang, Huazhong Yang:
On-Chip Instruction Generation for Cross-Layer CNN Accelerator on FPGA. ISVLSI 2019: 7-12 - [c224]Zheyu Liu, Zichen Fan, Qi Wei, Xing Wu, Fei Qiao, Ping Jin, Xinjun Liu, Chengliang Liu, Huazhong Yang:
Design of Switched-Current Based Low-Power PIM Vision System for IoT Applications. ISVLSI 2019: 181-186 - [c223]Zheyu Liu, Erxiang Ren, Li Luo, Qi Wei, Xing Wu, Xueqing Li, Fei Qiao, Xin-Jun Liu, Huazhong Yang:
A 1.8mW Perception Chip with Near-Sensor Processing Scheme for Low-Power AIoT Applications. ISVLSI 2019: 447-452 - [c222]Changlu Liu, Tianxiang Lan, Qin Li, Kaige Jia, Yidian Fan, Xing Wu, Fei Qiao, Wei Qi, Xin-Jun Liu, Huazhong Yang:
Energy-efficient Analog Processing Architecture for Direction of Arrival with Microphone Array. ISVLSI 2019: 507-512 - [c221]Juejian Wu, Mingyang Gu, Hongtao Zhong, Yunsong Tao, Fei Qiao, Huazhong Yang, Xueqing Li:
Enabling New Computing Paradigms with Emerging Symmetric-Access Memories. NANOARCH 2019: 1-6 - 2018
- [j94]Lixue Xia, Wenqin Huangfu, Tianqi Tang, Xiling Yin, Krishnendu Chakrabarty, Yuan Xie, Yu Wang, Huazhong Yang:
Stuck-at Fault Tolerance in RRAM Computing Systems. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(1): 102-115 (2018) - [j93]Longqiang Lai, Xueqing Li, Huazhong Yang:
Redundancy-bandwidth scalable techniques for signal-independent element transition rates in high-speed current-steering DACs. Int. J. Circuit Theory Appl. 46(5): 1006-1027 (2018) - [j92]Li Luo, Yakun Wu, Fei Qiao, Yi Yang, Qi Wei, Xiaobo Zhou, Yongkai Fan, Shuzheng Xu, Xinjun Liu, Huazhong Yang:
Design of FPGA-Based Accelerator for Convolutional Neural Network under Heterogeneous Computing Framework with OpenCL. Int. J. Reconfigurable Comput. 2018: 1785892:1-1785892:10 (2018) - [j91]Qin Li, Yuntao Wu, Huifeng Zhu, Qi Wei, Fei Qiao, Sheng Zhang, Huazhong Yang:
High linearity source-follower buffer based analog memory for analog convolutional neural network. Microelectron. J. 75: 147-152 (2018) - [j90]Guijin Wang, Wentao Li, Xuanwu Yin, Huazhong Yang:
All-in-focus with directional-max-gradient flow and labeled iterative depth propagation. Pattern Recognit. 77: 173-187 (2018) - [j89]Jingna Mao, Huazhong Yang, Yong Lian, Bo Zhao:
A Five-Tissue-Layer Human Body Communication Circuit Model Tunable to Individual Characteristics. IEEE Trans. Biomed. Circuits Syst. 12(2): 303-312 (2018) - [j88]Kaiyuan Guo, Lingzhi Sui, Jiantao Qiu, Jincheng Yu, Junbin Wang, Song Yao, Song Han, Yu Wang, Huazhong Yang:
Angel-Eye: A Complete Design Flow for Mapping CNN Onto Embedded FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(1): 35-47 (2018) - [j87]Lixue Xia, Boxun Li, Tianqi Tang, Peng Gu, Pai-Yu Chen, Shimeng Yu, Yu Cao, Yu Wang, Yuan Xie, Huazhong Yang:
MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(5): 1009-1022 (2018) - [j86]Xiaoming Chen, Qiaoyi Liu, Song Yao, Jia Wang, Qiang Xu, Yu Wang, Yongpan Liu, Huazhong Yang:
Hardware Trojan Detection in Third-Party Digital Intellectual Property Cores by Multilevel Feature Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(7): 1370-1383 (2018) - [j85]Yuliang Sun, Yu Wang, Huazhong Yang:
Bidirectional Database Storage and SQL Query Exploiting RRAM-Based Process-in-Memory Structure. ACM Trans. Storage 14(1): 8:1-8:19 (2018) - [j84]Jincheng Yu, Guangjun Ge, Yiming Hu, Xuefei Ning, Jiantao Qiu, Kaiyuan Guo, Yu Wang, Huazhong Yang:
Instruction Driven Cross-layer CNN Accelerator for Fast Detection on FPGA. ACM Trans. Reconfigurable Technol. Syst. 11(3): 22:1-22:23 (2018) - [j83]Jinyang Li, Yongpan Liu, Hehe Li, Zhe Yuan, Chenchen Fu, Jinshan Yue, Xiaoyu Feng, Chun Jason Xue, Jingtong Hu, Huazhong Yang:
PATH: Performance-Aware Task Scheduling for Energy-Harvesting Nonvolatile Processors. IEEE Trans. Very Large Scale Integr. Syst. 26(9): 1671-1684 (2018) - [c220]Huifeng Zhu, Qi Wei, Fei Qiao, Yi Yang, Xinjun Liu, Shuzheng Xu, Huazhong Yang:
CMOS Image Sensor Data-Readout Method for Convolutional Operations with Processing Near Sensor Architecture. APCCAS 2018: 528-531 - [c219]Yi Cai, Tianqi Tang, Lixue Xia, Ming Cheng, Zhenhua Zhu, Yu Wang, Huazhong Yang:
Training low bitwidth convolutional neural network on RRAM. ASP-DAC 2018: 117-122 - [c218]Wenyu Sun, Yuxuan Huang, Qinghang Zhao, Fei Qiao, Tsung-Yi Ho, Xiaojun Guo, Huazhong Yang, Yongpan Liu:
Mechanical strain and temperature aware design methodology for thin-film transistor based pseudo-CMOS logic array. ASP-DAC 2018: 645-650 - [c217]Yuxuan Huang, Jian Zhao, Wenyu Sun, Jingna Mao, Huazhong Yang, Yongpan Liu:
An Investigation on Inter-degeneration Effect in Body Channel Based Multi-node Wireless Power Transfer. BioCAS 2018: 1-4 - [c216]Cairong Zhang, Guijin Wang, Xinghao Chen, Huazhong Yang:
Bi-stream Region Ensemble Network: Promoting Accuracy in Fingertip Localization from Stereo Images. BMVC 2018: 314 - [c215]Kaige Jia, Zheyu Liu, Qi Wei, Fei Qiao, Xinjun Liu, Yi Yang, Hua Fan, Huazhong Yang:
Calibrating process variation at system level with in-situ low-precision transfer learning for analog neural network processors. DAC 2018: 12:1-12:6 - [c214]Yi Cai, Yujun Lin, Lixue Xia, Xiaoming Chen, Song Han, Yu Wang, Huazhong Yang:
Long live TIME: improving lifetime for training-in-memory engines by structured gradient sparsification. DAC 2018: 107:1-107:6 - [c213]Jilan Lin, Lixue Xia, Zhenhua Zhu, Hanbo Sun, Yi Cai, Hui Gao, Ming Cheng, Xiaoming Chen, Yu Wang, Huazhong Yang:
Rescuing memristor-based computing with non-linear resistance levels. DATE 2018: 407-412 - [c212]Jincheng Yu, Kaiyuan Guo, Yiming Hu, Xuefei Ning, Jiantao Qiu, Huizi Mao, Song Yao, Tianqi Tang, Boxun Li, Yu Wang, Huazhong Yang:
Real-time object detection towards high power efficiency. DATE 2018: 704-708 - [c211]Tianhao Huang, Guohao Dai, Yu Wang, Huazhong Yang:
HyVE: Hybrid vertex-edge memory hierarchy for energy-efficient graph processing. DATE 2018: 973-978 - [c210]Jingxuan Hou, Guijin Wang, Xinghao Chen, Jing-Hao Xue, Rui Zhu, Huazhong Yang:
Spatial-Temporal Attention Res-TCN for Skeleton-Based Dynamic Hand Gesture Recognition. ECCV Workshops (6) 2018: 273-286 - [c209]Zhourui Xia, Guijin Wang, Dapeng Fu, Haiqing Wang, Ming Chen, Pengwei Xie, Huazhong Yang:
Real-Time ECG Delineation with Randomly Selected Wavelet Transform Feature and Random Walk Estimation. EMBC 2018: 1-4 - [c208]Pengwei Xie, Guijin Wang, Chenshuang Zhang, Ming Chen, Huazhong Yang, Tingting Lv, Zhenhua Sang, Ping Zhang:
Bidirectional Recurrent Neural Network And Convolutional Neural Network (BiRCNN) For ECG Beat Classification. EMBC 2018: 2555-2558 - [c207]Ming Chen, GuiJin Wang, Pengwei Xie, Zhenhua Sang, Tingting Lv, Ping Zhang, Huazhong Yang:
Region Aggregation Network: Improving Convolutional Neural Network for ECG Characteristic Detection. EMBC 2018: 2559-2562 - [c206]Jingna Mao, Huazhong Yang, Yong Lian, Bo Zhao:
Channel Loss in Contactless Human Body Communication. EMBC 2018: 3762-3765 - [c205]Guohao Dai, Tianhao Huang, Yu Wang, Huazhong Yang, John Wawrzynek:
NewGraph: Balanced Large-Scale Graph Processing on FPGAs with Low Preprocessing Overheads. FCCM 2018: 208 - [c204]