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Alexey Glebov
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2000 – 2009
- 2009
- [c9]Alexander L. Stempkovsky
, Alexey Glebov, Sergey Gavrilov
:
Calculation of stress probability for NBTI-aware timing analysis. ISQED 2009: 714-718 - 2004
- [c8]Alexey Glebov, Sergey Gavrilov
, Vladimir Zolotov, Chanhee Oh, Rajendran Panda, Murat R. Becer:
False-Noise Analysis for Domino Circuits. DATE 2004: 784-789 - [c7]Alexey Glebov, Sergey Gavrilov
, R. Soloviev, Vladimir Zolotov, Murat R. Becer, Chanhee Oh, Rajendran Panda:
Delay noise pessimism reduction by logic correlations. ICCAD 2004: 160-167 - 2003
- [c6]D. Nadezhin, Sergey Gavrilov, Alexey Glebov, Y. Egorov, Vladimir Zolotov, David T. Blaauw, Rajendran Panda, Murat R. Becer, Alexandre Ardelea, A. Patel:
SOI Transistor Model for Fast Transient Simulation. ICCAD 2003: 120128 - 2002
- [j1]Alexey Glebov, Sergey Gavrilov
, David T. Blaauw, Vladimir Zolotov:
False-noise analysis using logic implications. ACM Trans. Design Autom. Electr. Syst. 7(3): 474-498 (2002) - [c5]Alexey Glebov, Sergey Gavrilov
, David T. Blaauw, Vladimir Zolotov, Rajendran Panda, Chanhee Oh:
False-Noise Analysis Using Resolution Method. ISQED 2002: 437-442 - 2001
- [c4]Alexey Glebov, Sergey Gavrilov
, David T. Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov:
False-Noise Analysis using Logic Implications. ICCAD 2001: 515-
1990 – 1999
- 1997
- [c3]Sergey Gavrilov, Alexey Glebov, Sergey G. Rusakov
, David T. Blaauw, Larry G. Jones, Gopalakrishnan Vijayan:
Fast power loss calculation for digital static CMOS circuits. ED&TC 1997: 411-415 - [c2]Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David T. Blaauw:
Library-less synthesis for static CMOS combinational logic circuits. ICCAD 1997: 658-662 - 1995
- [c1]Alexey Glebov, David T. Blaauw, Larry G. Jones:
Transistor reordering for low power CMOS gates using an SP-BDD representation. ISLPD 1995: 161-166
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