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2020 – today
- 2023
[c7]Guillem López-Paradís
, Balaji Venu, Adrià Armejach, Miquel Moretó:
Characterization of a Coherent Hardware Accelerator Framework for SoCs. SAMOS 2023: 91-106- 2022
- [c6]Matteo Andreozzi, Giacomo Gabrielli, Balaji Venu, Giacomo Travaglini:
Industrial Challenge 2022: A High-Performance Real-Time Case Study on Arm. ECRTS 2022: 1:1-1:15
2010 – 2019
- 2018
- [j2]Xabier Iturbe, Balaji Venu, Juergen Jagst, Emre Ozer, Peter Harrod, Chris Turner, John Penton:
Addressing Functional Safety Challenges in Autonomous Vehicles with the Arm TCL S Architecture. IEEE Des. Test 35(3): 7-14 (2018) - [j1]Xabier Iturbe, Balaji Venu, Emre Ozer, Jean-Luc Poupat, Gregoire Gimenez, Hans-Ulrich Zurek:
The Arm Triple Core Lock-Step (TCLS) Processor. ACM Trans. Comput. Syst. 36(3): 7:1-7:30 (2018) - [c5]Emre Ozer, Balaji Venu, Xabier Iturbe, Shidhartha Das, Spyros Lyberis, John Biggs, Peter Harrod, John Penton:
Error Correlation Prediction in Lockstep Processors for Safety-Critical Systems. MICRO 2018: 737-748 - 2017
- [c4]Xabier Iturbe, Balaji Venu, John Penton, Emre Ozer:
A "high resilience" mode to minimize soft error vulnerabilities in ARM cortex-R CPU pipelines: work-in-progress. CASES 2017: 6:1-6:2 - 2016
- [c3]Xabier Iturbe, Balaji Venu, Emre Ozer:
Soft error vulnerability assessment of the real-time safety-related ARM Cortex-R5 CPU. DFT 2016: 91-96 - [c2]Xabier Iturbe, Balaji Venu, Emre Ozer, Shidhartha Das:
A Triple Core Lock-Step (TCLS) ARM® Cortex®-R5 Processor for Safety-Critical and Ultra-Reliable Applications. DSN Workshops 2016: 246-249 - 2012
- [c1]Balaji Venu, Ashwani Singh:
Formal verification methodology considerations for network on chips. ICACCI 2012: 220-225 - 2011
- [i1]Balaji Venu:
Multi-core processors - An overview. CoRR abs/1110.3535 (2011)
Coauthor Index
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